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  1. Jun 02, 2006
    • Lennert Buytenhek's avatar
      [ARM] 3540/1: ixp23xx: deal with gap in interrupt bitmasks · ec8510f6
      Lennert Buytenhek authored 
      

Patch from Lennert Buytenhek

On the ixp23xx, the microengine thread interrupt sources are numbered
56..119, but their mask/status bits are located in bit positions 64..127
in the various registers in the interrupt controller (bit positions
56..63 are unused.)

We don't deal with this, so currently, when asked to enable IRQ 64, we
will enable IRQ 56 instead.

The only interrupts >= 64 are the thread interrupt sources, and there
are no in-tree users of those yet, so this is fortunately not a big
problem, but this needs fixing anyway.

Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ec8510f6
  3. May 31, 2006
  5. May 17, 2006
    • Thomas Gleixner's avatar
      [ARM] 3530/1: PXA Mainstone: prevent double enable_irq() in pcmcia · ec64152f
      Thomas Gleixner authored 
      

Patch from Thomas Gleixner

The mainstone board pcmcia interrupt have been enabled via setup_irq()
and the following socket check calls enable_irq again. Set the NOAUTOEN flag so the interrupt is not automatically enabled in setup_irq()

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarNicolas Pitre <nico@cam.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ec64152f
    • Dimitry Andric's avatar
      [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction · c3fb0416
      Dimitry Andric authored 
      

Patch from Dimitry Andric

In arch/arm/mach-s3c2410/sleep.S, the coprocessor registers are saved at
suspend time, and restored at resume time. However, an undefined
instruction is used when attempting to restore a non-existent "auxiliary
control register".  This leads to a crash on S3C2412, which has an ARM926
core instead of an ARM920.

At suspend time, the following fragment runs:

	mrc	p15, 0, r7, c2, c0, 0	@ translation table base address
	mrc	p15, 0, r8, c2, c0, 0	@ auxiliary control register
	mrc	p15, 0, r9, c1, c0, 0	@ control register

and at resume time, the following fragment runs:

	mcr	p15, 0, r7, c2, c0, 0		@ translation table base
	mcr	p15, 0, r8, c1, c1, 0		@ auxilliary control
	...
	mcr	p15, 0, r9, c1, c0, 0		@ turn on MMU, etc

There are several problems with these fragments:
1. The ARM920 and ARM926 cores don't have any "auxiliary control
   register", at least not according to the ARM920 and ARM926 TRM's.
2. The 2nd line of suspend erroneously saves the c2 register again.
3. This saved c2 value is restored using an undefined instruction.  For
   some reason this does not crash on ARM920, but does crash on ARM926.

The following patch fixes all these problems.

Signed-off-by: default avatarDimitry Andric <dimitry@andric.com>
Yes, this looks sensible

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      c3fb0416
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