- Jan 27, 2016
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Marcus Cooper authored
Itead have a core module board that can be populated with either an Allwinner A10 or A20 SoC. This patch creates a common dtsi which these boards can use. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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- Jan 24, 2016
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Chen-Yu Tsai authored
mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Chen-Yu Tsai authored
mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support. Signed-off-by:
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Chen-Yu Tsai authored
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by:
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Chen-Yu Tsai authored
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by:
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Chen-Yu Tsai authored
According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC. Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal voltage sensing, and "cap-mmc-hw-reset" to denote this instance can use eMMC hardware reset. Signed-off-by:
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Chen-Yu Tsai authored
mmc2 and mmc3 are available on the same pins, with different mux values. However, only mmc3 supports 8 bit DDR transfer modes. Since preference for mmc3 over mmc2 is due to DDR transfer modes, just set the drive strength to 40mA, which is needed for DDR. This pinmux setting also includes the hardware reset pin for emmc. Signed-off-by:
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Chen-Yu Tsai authored
sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA trigger levels can be increased. Also, the mmc module clock parent has a higher clock rate, and the sample and output delay phases are different. Signed-off-by:
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Chen-Yu Tsai authored
mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support. Signed-off-by:
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Maxime Ripard authored
The current DT doesn't have a phandle to the CPU regulator in the CPU node, which disables the CPU voltage scaling entirely. Add that phandle. Signed-off-by: -
Chen-Yu Tsai authored
Cubietruck Plus is a A83T/H8 based development board. The board has standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet, WiFi, headphone out / mic in, and various GPIO headers. The board also has an EEPROM on i2c0 which holds the MAC address. Signed-off-by:
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Chen-Yu Tsai authored
The A83T, like previous Allwinner SoCs, has a watchdog as part of its timer block. Add a device node for it. Signed-off-by:
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Vishnu Patekar authored
A83T timer is compatible with that of earlier SOCs. Just add timer node to enable and re-use it. Signed-off-by:
Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by:
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Vishnu Patekar authored
H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner. It has UART, ethernet, USB, HDMI, etc ports on it. A83T patches are tested on this board. It has UART, ethernet, USB, HDMI, etc ports on it. For FEL mode it needs USB A-A(Male) cable. I used uart0 which is multiplexed to microsd pins PF2 and PF4. Enabled UART0 Header(PB9, PB10 pins). Signed-off-by:
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Vishnu Patekar authored
Allwinner A83T is new octa-core cortex-a7 SOC. This adds the basic dtsi, the clocks differs from earlier sun8i SOCs. Signed-off-by:
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Hans de Goede authored
Add a node describing the focaltech ft5306de4 touchscreen found on inet97fv2 tablets. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Hans de Goede authored
Add a node describing the focaltech ft5306de4 touchscreen found on chuwi-v7-cw0825 tablets. Signed-off-by:
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Hans de Goede authored
Add a node describing the focaltech ft5406ee8 touchscreen found on inet-9f-rev03 / qware qw tb-g100 tablets. Signed-off-by:
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Alban Bedel authored
As most platforms implement the PROM serial interface prom_putchar() add a simple bridge to allow re-using this code for zboot. Signed-off-by:
Alban Bedel <albeu@free.fr> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11811/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Alban Bedel authored
Add dummy.o to the targets list, and fill targets automatically from $(vmlinuzobjs) to avoid having to maintain two lists. When building with XZ compression copy ashldi3.c to the build directory to use a different object file for the kernel and zboot. Without this the same object file need to be build with different flags which cause a rebuild at every run. Signed-off-by:
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Florian Fainelli authored
Allow BMIPS_GENERIC supported platforms to build GPIO controller drivers. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Dragan Stancevic <dragan.stancevic@gmail.com> Cc: cernekee@gmail.com Cc: jaedon.shin@gmail.com Cc: gregory.0xf0@gmail.com Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12019/ Signed-off-by:
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Simon Arlott authored
Remove bcm63xx_nvram_get_psi_size() as it now has no users. Signed-off-by:
Simon Arlott <simon@fire.lp0.eu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Cc: MIPS Mailing List <linux-mips@linux-mips.org> Cc: MTD Maling List <linux-mtd@lists.infradead.org> Patchwork: https://patchwork.linux-mips.org/patch/11836/ Signed-off-by:
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Simon Arlott authored
Move Broadcom BCM963xx image tag data structure to include/linux/ so that drivers outside of mach-bcm63xx can use it. Signed-off-by:
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Simon Arlott authored
Use the common definition of the nvram structure from the header file include/linux/bcm963xx_nvram.h instead of maintaining a separate copy. Read the version 5 size of nvram data from memory and then call the new checksum verification function from the header file. Signed-off-by:
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James Hogan authored
Add missing newline to end of kvm_err string when guest PMAP couldn't be allocated. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11896/ Signed-off-by:
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James Hogan authored
The header arch/mips/kvm/opcode.h defines a few extra opcodes which aren't in arch/mips/include/uapi/asm/inst.h. There's nothing KVM specific about them, so lets move them into inst.h where they belong and delete the header. Note that mfmcz_op is renamed to mfmc0_op to match the instruction set manual, and wait_op was already added to inst.h in commit b0a3eae2 ("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1. Signed-off-by:
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James Hogan authored
Drop the custom cache operation code definitions used by KVM for emulating guest CACHE instructions, and switch to use the existing definitions in <asm/cacheops.h>. Signed-off-by:
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James Hogan authored
Most of the cache op codes defined in cacheops.h are split into a 2-bit cache identifier, and a 3-bit cache op code which does largely the same thing semantically regardless of the cache identifier. To allow the use of these definitions by KVM for decoding cache ops, break the definitions down into parts where it makes sense to do so, and add masks for the Cache and Op field within the cache op. Signed-off-by:
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James Hogan authored
The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by:
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James Hogan authored
Add a few missing trap codes. [ralf@linux-mips.org: Drop removal of exception codes. I don't care what the incomplete architecture spec says; it can't change existing hardware and VCEI is supported indeed.] Signed-off-by:
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James Hogan authored
Move the Cause.ExcCode trap code definitions from kvm_host.h to mipsregs.h, since they describe architectural bits rather than KVM specific constants, and change the prefix from T_ to EXCCODE_. Signed-off-by:
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James Hogan authored
The module init and exit functions have no need to be global, so make them static. Signed-off-by:
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James Hogan authored
When calculating the offsets into the commpage for dynamically translated mtc0/mfc0 guest instructions, multiple offsetof()s are added together to find the offset of the specific register in the mips_coproc, within the commpage. Simplify each of these cases to a single offsetof() to find the offset of the specific register within the commpage. Signed-off-by:
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James Hogan authored
Export symbols only to GPL modules to match other KVM symbols in virt/kvm/ and arch/*/kvm/. Signed-off-by:
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James Hogan authored
The function kvm_mips_host_tlb_inv_index() is unused, so drop it completely. Signed-off-by:
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James Hogan authored
The CAUSEB_DC and CAUSEF_DC definitions used by KVM are defined in asm/kvm_host.h, but all the other Cause register field definitions are found in asm/mipsregs.h. Lets reunite the DC bit definitions with its friends in mipsregs.h. Signed-off-by:
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James Hogan authored
Some definitions in the MIPS asm/kvm_host.h are completely unused, so lets drop them. MS_TO_NS is no longer used since commit e30492bb ("MIPS: KVM: Rewrite count/compare timer emulation"). The others don't appear ever to have been used. Signed-off-by:
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James Hogan authored
A bunch of misc whitespace and style fixes within arch/mips/kvm/. Signed-off-by:
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Joshua Henderson authored
This adds an initial default config that enables all available PIC32 drivers and is enough for booting a PIC32MZDA Starter Kit. Signed-off-by:
Joshua Henderson <joshua.henderson@microchip.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12105/ Signed-off-by:
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Joshua Henderson authored
This adds basic DTS configuration for the PIC32MZDA chip and in turn the PIC32MZDA Starter Kit. Signed-off-by:
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