- Feb 29, 2016
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Daniel Sanders authored
The target independent parts of the LLVM Lexer considers 'fault@function' to be a single token representing the 'fault' symbol with a 'function' modifier. However, this is not the case in the .type directive where 'function' refers to STT_FUNC from the ELF standard. Although GAS accepts it, '.type symbol@function' is an undocumented form of this directive. The documentation specifies a comma between the symbol and '@function'. Signed-off-by:
Scott Egerton <Scott.Egerton@imgtec.com> Signed-off-by:
Daniel Sanders <daniel.sanders@imgtec.com> Reviewed-by:
Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12587/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- Feb 11, 2016
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Daniel Wagner authored
Depending on the configuration either the 32 or 64 bit version of elf_check_arch() is defined. parse_crash_elf{32|64}_headers() does some basic verification of the ELF header via vmcore_elf{32|64}_check_arch() which happen to map to elf_check_arch(). Since the implementation 32 and 64 bit version of elf_check_arch() differ, we use the wrong type: In file included from include/linux/elf.h:4:0, from fs/proc/vmcore.c:13: fs/proc/vmcore.c: In function 'parse_crash_elf64_headers': >> arch/mips/include/asm/elf.h:228:23: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types] struct elfhdr *__h = (hdr); \ ^ include/linux/crash_dump.h:41:37: note: in expansion of macro 'elf_check_arch' #define vmcore_elf64_check_arch(x) (elf_check_arch(x) || vmcore_elf_check_arch_cross(x)) ^ fs/proc/vmcore.c:1015:4: note: in expansion of macro 'vmcore_elf64_check_arch' !vmcore_elf64_check_arch(&ehdr) || ^ Therefore, we rather define vmcore_elf{32|64}_check_arch() as a basic machine check and use it also in binfm_elf?32.c as well. Signed-off-by:Daniel Wagner <daniel.wagner@bmw-carit.de> Suggested-by:
Fengguang Wu <fengguang.wu@intel.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12529/ Signed-off-by:
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- Feb 09, 2016
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Paul Burton authored
Commit c014d164 ("MIPS: Add platform callback before initializing the L2 cache") added a platform_early_l2_init function in order to allow platforms to probe for the CM before L2 initialisation is performed, so that CM GCRs are available to mips_sc_probe. That commit actually fails to do anything useful, since it checks mips_cm_revision to determine whether it should call mips_cm_probe but the result of mips_cm_revision will always be 0 until mips_cm_probe has been called. Thus the "early" mips_cm_probe call never occurs. Fix this & drop the useless weak platform_early_l2_init function by simply calling mips_cm_probe from setup_arch. For platforms that don't select CONFIG_MIPS_CM this will be a no-op, and for those that do it removes the requirement for them to call mips_cm_probe manually (although doing so isn't harmful for now). Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Rob Herring <robh@kernel.org> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Jaedon Shin <jaedon.shin@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12475/ Signed-off-by:
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- Feb 05, 2016
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Ralf Baechle authored
Signed-off-by:
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- Feb 02, 2016
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Maciej W. Rozycki authored
Fix the code to fetch and decode the whole 32-bit instruction. This only really matters with the `noulri' kernel parameter as all microMIPS processors are supposed to have all the hardware registers we support. Signed-off-by:
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Maciej W. Rozycki authored
In the regular MIPS instruction set RDHWR is encoded with the SPECIAL3 (011111) major opcode. Therefore it cannot trigger the CpU (Coprocessor Unusable) exception, and certainly not for coprocessor 0, as the opcode does not overlap with any of the older ISA reservations, i.e. LWC0 (110000), SWC0 (111000), LDC0 (110100) or SDC0 (111100). The closest match might be SDC3 (111111), possibly causing a CpU #3 exception, however our code does not handle it anyway. A quick check with a MIPS I and a MIPS III processor: CPU0 revision is: 00000220 (R3000) CPU0 revision is: 00000440 (R4400SC) indeed indicates that the RI (Reserved Instruction) exception is triggered. It's only LL and SC that require emulation in the CpU #0 exception handler as they reuse the LWC0 and SWC0 opcodes respectively. In the microMIPS instruction set RDHWR is mandatory and triggering the RI exception is required on unimplemented or disabled register accesses. Therefore emulating the microMIPS instruction in the CpU #0 exception handler is not required either. Signed-off-by:
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- Feb 01, 2016
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James Hogan authored
start_thread() (called for execve(2)) clears the TIF_USEDFPU flag without atomically disabling the FPU. With a preemptive kernel, an unfortunately timed preemption after this could result in another task (or KVM guest) being scheduled in with the FPU still enabled, since lose_fpu_inatomic() only turns it off if TIF_USEDFPU is set. Use lose_fpu(0) instead of the separate FPU / MSA management, which should do the right thing (drop FPU properly and atomically without saving state) and will be more future proof. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
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- Jan 24, 2016
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James Hogan authored
The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by:
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James Hogan authored
The cp0_tcstatus member of struct pt_regs was removed along with the rest of SMTC in v3.16, commit b633648c ("MIPS: MT: Remove SMTC support"), however recent uprobes support in v4.3 added back a reference to it in the regoffset_table[] in ptrace.c. Remove it. Signed-off-by:
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Linus Walleij authored
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11923/ Signed-off-by:
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Jaedon Shin authored
Change the CONFIG_MIPS_CMDLINE_EXTEND to CONFIG_MIPS_CMDLINE_DTB_EXTEND to resolve the EXTEND_WITH_PROM macro. Signed-off-by:
Jaedon Shin <jaedon.shin@gmail.com> Fixes: 2024972e ("MIPS: Make the kernel arguments from dtb available") Reviewed-by:
Alexander Sverdlin <alexander.svedlin@gmail.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11909/ Signed-off-by:
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Matt Redfearn authored
The kernel currently assumes that a core will start up in legacy mode using the exception base provided through the CM GCR registers. If a core has been configured in hardware to start in EVA mode, these assumptions will fail. This patch ensures that secondary cores are initialized to meet these assumptions. Signed-off-by:
Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by:
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Huacai Chen authored
While synchronization, count register will go backwards for the master. If synchronise_count_master() runs before synchronise_count_slave(), skew becomes even more. The skew is very harmful for CPU hotplug (CPU0 do synchronization with CPU1, then CPU0 do synchronization with CPU2 and CPU0's count goes backwards, so it will be out of sync with CPU1). After the commit cf9bfe55 (MIPS: Synchronize MIPS count one CPU at a time), we needn't evaluate count_reference at the beginning of synchronise_count_master() any more. Thus, we evaluate the initcount (It seems like count_reference is redundant) in the 2nd loop. Since we write the count register in the last loop, we don't need additional barriers (the existing memory barriers are enough). Moreover, I think we loop 3 times is enough to get a primed instruction cache, this can also get less skew than looping 5 times. Comments are also updated in this patch. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/12163/ Signed-off-by:
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- Jan 19, 2016
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Maciej W. Rozycki authored
Add an `ieee754=' kernel parameter to control IEEE Std 754 conformance mode. Use separate flags copied from the respective CPU feature flags, and adjusted according to the conformance mode selected, to make binaries requesting individual NaN encoding modes accepted or rejected as needed. Update the initial setting for FCSR and, in the full FPU emulation mode, its read-only mask accordingly. Accept the mode selection requested for legacy processors as well. As with the EF_MIPS_NAN2008 ELF file header flag adjust both ABS2008 and NAN2008 bits at the same time, to match the choice made for hardware currently implemented. Signed-off-by:
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Maciej W. Rozycki authored
Determine the presence of and the amount of control available over IEEE Std 754-2008 features. In the case of a hardware FPU being used examine the FIR register for the presence of the HAS2008 bit and then the FCSR register for the writability of the ABS2008 and NAN2008 bits and the hardwired state of each of these bits if read-only. Update the initial FCSR contents used for threads and the FCSR writability mask accordingly. For full FPU emulation and MIPS32 or MIPS64 processors make the FCSR ABS2008 and NAN2008 bits writable. Signed-off-by:
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Maciej W. Rozycki authored
Handle the EF_MIPS_NAN2008 ELF file header flag and refuse execution where there is no support in the FPU for the NaN encoding mode requested by a binary invoked. Ensure that the setting of the bit in the binary matches one in any intepreter used. Set the thread's initial FCSR contents according to the value of the EF_MIPS_NAN2008. Set the values of the FCSR ABS2008 and NAN2008 bits both to the same value if possible, to take the approach taken with existing FPU hardware into account. As of now all implementations have both bits hardwired to the same value, that is both are fixed at 0 or both are fixed at 1, even though the architecture allows for implementations where the amount of control implemented with each of these two individual bits is independent of each other. Signed-off-by:
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Maciej W. Rozycki authored
Also pass any interpreter's file header to `arch_check_elf' so that any architecture handler can have a look at it if needed. Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Acked-by:
Al Viro <viro@zeniv.linux.org.uk> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11478/ Signed-off-by:
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Maciej W. Rozycki authored
Implement IEEE Std 754-2008 NaN encoding wired to the state of the FCSR.NAN2008 bit. Make the interpretation of the quiet bit in NaN data as follows: * in the legacy mode originally defined by the MIPS architecture the value of 1 denotes an sNaN whereas the value of 0 denotes a qNaN, * in the 2008 mode introduced with revision 5 of the MIPS architecture the value of 0 denotes an sNaN whereas the value of 1 denotes a qNaN, following the definition of the preferred NaN encoding introduced with IEEE Std 754-2008. In the 2008 mode, following the requirement of the said standard, quiet an sNaN where needed by setting the quiet bit to 1 and leaving all the NaN payload bits unchanged. Update format conversion operations according to the rules set by IEEE Std 754-2008 and the MIPS architecture. Specifically: * propagate NaN payload bits through conversions between floating-point formats such that as much information as possible is preserved and specifically a conversion from a narrower format to a wider format and then back to the original format does not change a qNaN payload in any way, * conversions from a floating-point to an integer format where the source is a NaN, infinity or a value that would convert to an integer outside the range of the result format produce, under the default exception handling, the respective values defined by the MIPS architecture. In full FPU emulation set the FIR.HAS2008 bit to 1, however do not make any further FCSR bits writable. Signed-off-by:
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Maciej W. Rozycki authored
Allocate CPU option bits and define macros for the legacy-NaN and 2008-NaN IEEE Std 754 MIPS architecture features. Unconditionally mark the legacy-NaN feature as present across hardware and emulated floating-point configurations. Signed-off-by:
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Maciej W. Rozycki authored
Rewrite `arch_elf_pt_proc' and `arch_check_elf' using a union to access the ELF file header. Signed-off-by:
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- Dec 22, 2015
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Paul Burton authored
Commit 977e043d ("MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2") leads to .set mips64r2 directives being present in 32 bit (ie. CONFIG_32BIT=y) kernels. This is incorrect & leads to MIPS64 instructions being emitted by the assembler when expanding pseudo-instructions. For example the "move" instruction can legitimately be expanded to a "daddu". This causes problems when the kernel is run on a MIPS32 CPU, as CONFIG_32BIT kernels of course often are... Fix this by dropping the .set <ISA> directives entirely now that Kconfig should be ensuring that kernels including this code are built with a suitable -march= compiler flag. Signed-off-by:
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James Hogan authored
__clear_user() (and clear_user() which uses it), always access the user mode address space, which results in EVA store instructions when EVA is enabled even if the current user address limit is KERNEL_DS. Fix this by adding a new symbol __bzero_kernel for the normal kernel address space bzero in EVA mode, and call that from __clear_user() if eva_kernel_access(). Signed-off-by:
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- Dec 04, 2015
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Rusty Russell authored
Makes it easier to handle init vs core cleanly, though the change is fairly invasive across random architectures. It simplifies the rbtree code immediately, however, while keeping the core data together in the same cachline (now iff the rbtree code is enabled). Acked-by:
Peter Zijlstra <peterz@infradead.org> Reviewed-by:
Josh Poimboeuf <jpoimboe@redhat.com> Signed-off-by:
Rusty Russell <rusty@rustcorp.com.au> Signed-off-by:
Jiri Kosina <jkosina@suse.cz>
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- Nov 12, 2015
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Aurelien Jarno authored
While the 5KE processors have never been taped out, they exists though a CP0.PRId and experimental RTLs or QEMU implementations. Add a case entry in the idle code, as they can use the standard idle loop like the 5K processors. Signed-off-by:
Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11099/ Signed-off-by:
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Aaro Koskinen authored
For bootloaders that support booting only ELF kernels and load only ELF segments to memory there is no easy way to supply DTB without kernel recompilation. For that purpose, create a section called .appended_dtb that can be later updated with board-specific DTB using binutils e.g. at kernel installation time. Signed-off-by:
Aaro Koskinen <aaro.koskinen@nokia.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11114/ Signed-off-by:
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- Nov 11, 2015
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Jonas Gorski authored
Similar to how arm allows using selecting between bootloader arguments, dtb arguments and both, allow to select them on mips. But since we have less control over the place of the dtb do not modify it but instead use the boot_command_line for merging them. The default is "use bootloader arguments" to keep the current behaviour as default. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Cc: Jayachandran C <jchandra@broadcom.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11284/ Signed-off-by:
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Aaro Koskinen authored
Add LATENCYTOP support for MIPS. Tested on OCTEON. Signed-off-by:
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Alex Smith authored
Add user-mode implementations of gettimeofday() and clock_gettime() to the VDSO. This is currently usable with 2 clocksources: the CP0 count register, which is accessible to user-mode via RDHWR on R2 and later cores, or the MIPS Global Interrupt Controller (GIC) timer, which provides a "user-mode visible" section containing a mirror of its counter registers. This section must be mapped into user memory, which is done below the VDSO data page. When a supported clocksource is not in use, the VDSO functions will return -ENOSYS, which causes libc to fall back on the standard syscall path. When support for neither of these clocksources is compiled into the kernel at all, the VDSO still provides clock_gettime(), as the coarse realtime/monotonic clocks can still be implemented. However, gettimeofday() is not provided in this case as nothing can be done without a suitable clocksource. This causes the symbol lookup to fail in libc and it will then always use the standard syscall path. This patch includes a workaround for a bug in QEMU which results in RDHWR on the CP0 count register always returning a constant (incorrect) value. A fix for this has been submitted, and the workaround can be removed after the fix has been in stable releases for a reasonable amount of time. A simple performance test which calls gettimeofday() 1000 times in a loop and calculates the average execution time gives the following results on a Malta + I6400 (running at 20MHz): - Syscall: ~31000 ns - VDSO (GIC): ~15000 ns - VDSO (CP0): ~9500 ns [markos.chandras@imgtec.com: - Minor code re-arrangements in order for mappings to be made in the order they appear to the process' address space. - Move do_{monotonic, realtime} outside of the MIPS_CLOCK_VSYSCALL ifdef - Use gic_get_usm_range so we can do the GIC mapping in the arch/mips/kernel/vdso instead of the GIC irqchip driver] Signed-off-by:Alex Smith <alex.smith@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11338/ Signed-off-by:
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Alex Smith authored
Add an initial implementation of a proper (i.e. an ELF shared library) VDSO. With this commit it does not export any symbols, it only replaces the current signal return trampoline page. A later commit will add user implementations of gettimeofday()/clock_gettime(). To support both new toolchains and old ones which don't generate ABI flags section, we define its content manually and then use a tool (genvdso) to patch up the section to have the correct name and type. genvdso also extracts symbol offsets ({,rt_}sigreturn) needed by the kernel, and generates a C file containing a "struct mips_vdso_image" containing both the VDSO data and these offsets. This C file is compiled into the kernel. On 64-bit kernels we require a different VDSO for each supported ABI, so we may build up to 3 different VDSOs. The VDSO to use is selected by the mips_abi structure. A kernel/user shared data page is created and mapped below the VDSO image. This is currently empty, but will be used by the user time function implementations which are added later. [markos.chandras@imgtec.com: - Add more comments - Move abi detection in genvdso.h since it's the get_symbol function that needs it. - Add an R6 specific way to calculate the base address of VDSO in order to avoid the branch instruction which affects performance. - Do not patch .gnu.attributes since it's not needed for dynamic linking. - Simplify Makefile a little bit. - checkpatch fixes - Restrict VDSO support for binutils < 2.25 for pre-R6 - Include atomic64.h for O32 variant on MIPS64] Signed-off-by: -
Paul Burton authored
Extend the existing support for Hardware Table Walking (HTW) to MIPS64 systems by supporting PMDs & setting the pointer size bit in PWSize, then ceasing to blacklist HTW on MIPS64 systems. Signed-off-by:
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Paul Burton authored
Prior to release 6 of the MIPS architecture it has been implementation dependent whether masked interrupts cause a wait instruction to return, so the kernel has effectively had to maintain a whitelist of cores upon which it is safe to use the r4k_wait_irqoff cpu_wait implementation. With MIPSr6 this is no longer implementation dependent and r4k_wait_irqoff can always be used. Remove the existing I6400 case which will no longer ever be hit, and was incorrect anyway since I6400 & r6 in general doesn't have the WII bit. Signed-off-by:
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Paul Burton authored
Ensure the update to which core the core-other GCR regions reflect has taken place before any core-other GCRs are accessed by placing a memory barrier (sync instruction) between the write to the core-other registers and any such GCR accesses. Signed-off-by:
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Paul Burton authored
Document that CPC core-other accesses must take place within the bounds of the CM lock, and begin using the CM lock functions where we access the GCRs of other cores. This is required because with CM3 the CPC began using GCR_CL_OTHER instead of CPC_CL_OTHER. Signed-off-by:
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Paul Burton authored
Introduce mips_cm_lock_other & mips_cm_unlock_other, mirroring the existing CPC equivalents, in order to lock access from the current core to another via the core-other GCR region. This hasn't been required in the past but with CM3 the CPC starts using GCR_CL_OTHER rather than CPC_CL_OTHER and this will be required for safety. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
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Paul Burton authored
When debugging core bringup it is useful to see the state of the CPC sequencer, so output that value if the core hasn't started within a reasonable amount of time (1 second). This avoids simply appearing to the user to hang if a secondary core fails to start. Signed-off-by:
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Paul Burton authored
The Config1 register is architecturally defined as required, and is thus present in all systems which may make use of cps-vec.S. Skip the check for its presence via the Config.M bit. Signed-off-by:
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Paul Burton authored
Rather than patching the start of mips_cps_core_entry to provide the base address of the CM GCRs, simply read that base address from the cop0 CMGCRBase register, converting from the physical address to an uncached virtual address. Signed-off-by:
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Paul Burton authored
Provide support for outputting early debug information, in the form of various register values should an exception occur, during the early bringup of secondary cores. This code requires an ns16550-compatible UART accessible from the secondary core, and is written in assembly due to the environment in which such early exceptions occur where way may not have a stack, be coherent or even have initialised caches. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by:
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- Nov 10, 2015
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David Daney authored
OCTEON Pre-SDK-1.8.1 bootloaders can not handle PT_NOTE program headers, so do not emit them. Before the patch: $ readelf --program-headers octeon-vmlinux Elf file type is EXEC (Executable file) Entry point 0xffffffff815d09d0 There are 2 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000001000 0xffffffff81100000 0xffffffff81100000 0x0000000000b57f80 0x0000000001b86360 RWE 1000 NOTE 0x00000000004e02e0 0xffffffff815df2e0 0xffffffff815df2e0 0x0000000000000024 0x0000000000000024 R 4 After the patch: $ readelf --program-headers octeon-vmlinux Elf file type is EXEC (Executable file) Entry point 0xffffffff815d09d0 There are 1 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000001000 0xffffffff81100000 0xffffffff81100000 0x0000000000b57f80 0x0000000001b86360 RWE 1000 The patch was tested on DSR-1000N router. Signed-off-by:David Daney <ddaney@caviumnetworks.com> Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11403/ Signed-off-by:
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Aaro Koskinen authored
Discard .MIPS.abiflags from vmlinux. It's not needed and will cause issues e.g. with old OCTEON bootloaders that cannot tolerate additional program headers. Before the patch: $ readelf --program-headers octeon-vmlinux Elf file type is EXEC (Executable file) Entry point 0xffffffff815d09d0 There are 3 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align ABIFLAGS 0x00000000005e77f0 0xffffffff816e67f0 0xffffffff816e67f0 0x0000000000000018 0x0000000000000018 R 8 LOAD 0x0000000000001000 0xffffffff81100000 0xffffffff81100000 0x0000000000b57f80 0x0000000001b86360 RWE 1000 NOTE 0x00000000004e02e0 0xffffffff815df2e0 0xffffffff815df2e0 0x0000000000000024 0x0000000000000024 R 4 After the patch: $ readelf --program-headers octeon-vmlinux Elf file type is EXEC (Executable file) Entry point 0xffffffff815d09d0 There are 2 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000001000 0xffffffff81100000 0xffffffff81100000 0x0000000000b57f80 0x0000000001b86360 RWE 1000 NOTE 0x00000000004e02e0 0xffffffff815df2e0 0xffffffff815df2e0 0x0000000000000024 0x0000000000000024 R 4 Suggested-by:Matthew Fortune <matthew.fortune@imgtec.com> Suggested-by:
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