- Nov 10, 2010
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Felipe Contreras authored
Also, don't be picky about the location, which incidentally fixes the build since MEMBLOCK_REAL_LIMIT is gone on 2.6.37. arch/arm/plat-omap/devices.c: In function 'omap_dsp_reserve_sdram_memblock': arch/arm/plat-omap/devices.c:287: error: 'MEMBLOCK_REAL_LIMIT' undeclared (first use in this function) Signed-off-by:Felipe Contreras <felipe.contreras@gmail.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Omar Ramirez Luna <omar.ramirez@ti.com>
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- Nov 01, 2010
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Linus Walleij authored
This fixes an erroneous use of LSB first in the U300 machine, the PL022 used in U300 is a standard ARM core that doesn't support this bit so it should never have been set. Cc: Kevin Wells <wellsk40@gmail.com>OA Signed-off-by:
Linus Walleij <linus.walleij@stericsson.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Oct 30, 2010
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Yinghai Lu authored
Russ Anderson reported: | There is a regression that is causing a NULL pointer dereference | in free_irte when shutting down xpc. git bisect narrowed it down | to git commit d585d060(intr_remap: Simplify the code further), which | changed free_irte(). Reverse applying the patch fixes the problem. We need to use irq_remapped() for each irq instead of checking only intr_remapping_enabled as there might be non remapped irqs even when remapping is enabled. [ tglx: use cfg instead of retrieving it again. Massaged changelog ] Reported-bisected-and-tested-by:
Russ Anderson <rja@sgi.com> Signed-off-by:
Yinghai Lu <yinghai@kernel.org> Cc: Suresh Siddha <suresh.b.siddha@intel.com> LKML-Reference: <4CCBD511.40607@kernel.org> Signed-off-by:
Thomas Gleixner <tglx@linutronix.de>
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- Oct 29, 2010
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Vasily Khoruzhick authored
Register UDA1380 codec during H1940 machine init Signed-off-by:
Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by:
Ben Dooks <ben-linux@fluff.org>
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Vasily Khoruzhick authored
Current implementation of LCD and backlight power control functions is not complete, as result PDA consumes power in suspend. Fix this issue by managing state of some latch bits, just like WinMobile does. Signed-off-by:
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Jason Baron authored
Currently, text_poke_smp() passes a NULL as the third argument to __stop_machine(), which will only run stop_machine_text_poke() on 1 cpu. Change NULL -> cpu_online_mask, as stop_machine_text_poke() is intended to be run on all cpus. I actually didn't notice any problems with stop_machine_text_poke() only being called on 1 cpu, but found this via code inspection. Signed-off-by:
Jason Baron <jbaron@redhat.com> LKML-Reference: <20101028152026.GB2875@redhat.com> Acked-by:
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Acked-by:
Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Signed-off-by:
H. Peter Anvin <hpa@linux.intel.com>
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Abdoulaye Walsimou Gaye authored
Recent changes in s3c gpio break mini2440 board and may be others. The problem is that mach-mini2440.c: mini2440_init() (where we call s3c_gpio_setpull()) is called before s3c2440.c: s3c2440_init() (where we initialize s3c24xx_gpiocfg_default.set_pull function pointer). This causes dereferencing of NULL pointer at boot time and a kernel panic. Signed-off-by:
Abdoulaye Walsimou Gaye <awg@embtoolkit.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by:
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Abdoulaye Walsimou Gaye authored
* kconfig symbols defined in arch/arm/mach-s3c2440/Kconfig are only available when ARCH_S3C2410 is selected, so no need to make some of them depend on ARCH_S3C2410. * fix CPU_S3C24405B typo in "config S3C2440_DMA". * mini2440: remove unconditionally select of SND_S3C24XX_SOC_S3C24XX_UDA134X. Those fixes avoid the following warnings at make time: scripts/kconfig/qconf arch/arm/Kconfig warning: (MACH_MINI2440 && ARCH_S3C2410) selects SND_S3C24XX_SOC_S3C24XX_UDA134X which has unmet direct dependencies (SND_S3C24XX_SOC && ARCH_S3C2410) warning: (CPU_S3C2440 && ARCH_S3C2410 && S3C2410_DMA) selects S3C2440_DMA which has unmet direct dependencies (ARCH_S3C2410 && CPU_S3C24405B) warning: (CPU_S3C2440 && ARCH_S3C2410 || CPU_S3C2442 && ARCH_S3C2410) selects CPU_S3C244X which has unmet direct dependencies (!ARCH_S3C2410) Signed-off-by:
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Daniel Walker authored
These two config options don't exist, and aren't ever going to. So I simply delete them. Signed-off-by:Daniel Walker <dwalker@codeaurora.org>
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Daniel Walker authored
If the board has a debug uart the user is given a choice of which uart to use. The user can also select NONE, which means not to use one. In most of our header files when NONE is selected nothing is defined for MSM_DEBUG_UART_PHYS or MSM_DEBUG_UART_BASE. This causes a compile failure in debug-macro.S which expect something to be defined there. Example of the failure, arch/arm/kernel/built-in.o: In function `hexbuf': linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_PHYS' linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_BASE' This fixes the compile failure by adding an ifdef to debug-macro.S that removes all the debug uart code in the case of NONE. Signed-off-by: -
Daniel Walker authored
Originally there was an ifdef case to handle when no debug uart was selected. In commit 0ea12930 that case was removed which causes the following build failure, linux-2.6/arch/arm/kernel/debug.S: Assembler messages: linux-2.6/arch/arm/kernel/debug.S:174: Error: bad instruction `addruart r1,r2' linux-2.6/arch/arm/kernel/debug.S:176: Error: bad instruction `waituart r2,r3' linux-2.6/arch/arm/kernel/debug.S:177: Error: bad instruction `senduart r1,r3' linux-2.6/arch/arm/kernel/debug.S:178: Error: bad instruction `busyuart r2,r3' linux-2.6/arch/arm/kernel/debug.S:190: Error: bad instruction `addruart r1,r2' This is a partial revert to add back the case which was removed with two caveats. First the API for the addruart macro was updated, and the new addruart case now return 0xfff00000 so that a know IO mapping is created instead of a random one. Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jason Wang <jason77.wang@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by:
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Steven Rostedt authored
On i386 (not x86_64) early implementations of gcc would have a bug with asm goto causing it to produce code like the following: (This was noticed by Peter Zijlstra) 56 pushl 0 67 nopl jmp 0x6f popl jmp 0x8c 6f mov test je 0x8c 8c mov call *(%esp) The jump added in the asm goto skipped over the popl that matched the pushl 0, which lead up to a quick crash of the system when the jump was enabled. The nopl is defined in the asm goto () statement and when tracepoints are enabled, the nop changes to a jump to the label that was specified by the asm goto. asm goto is suppose to tell gcc that the code in the asm might jump to an external label. Here gcc obviously fails to make that work. The bug report for gcc is here: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46226 The bug only appears on x86 when not compiled with -maccumulate-outgoing-args. This option is always set on x86_64 and it is also the work around for a function graph tracer i386 bug. (See commit: 746357d6) This explains why the bug only showed up on i386 when function graph tracer was not enabled. This patch now adds a CONFIG_JUMP_LABEL option that is default off instead of using jump labels by default. When jump labels are enabled, the -maccumulate-outgoing-args will be used (causing a slightly larger kernel image on i386). This option will exist until we have a way to detect if the gcc compiler in use is safe to use on all configurations without the work around. Note, there exists such a test, but for now we will keep the enabling of jump label as a manual option. Archs that know the compiler is safe with asm goto, may choose to select JUMP_LABEL and enable it by default. Reported-by:Ingo Molnar <mingo@elte.hu> Cause-discovered-by:
Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Baron <jbaron@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: David Daney <ddaney@caviumnetworks.com> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: David Miller <davem@davemloft.net> Cc: Richard Henderson <rth@redhat.com> LKML-Reference: <1288028746.3673.11.camel@laptop> Signed-off-by:
Steven Rostedt <rostedt@goodmis.org>
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Dongdong Deng authored
commit 534af108(kgdb,kdb: individual register set and and get API) introduce dbg_get_reg/dbg_set_reg API for individual register get and set. This patch implement those APIs for ppc. Signed-off-by:
Dongdong Deng <dongdong.deng@windriver.com> Signed-off-by:
Jason Wessel <jason.wessel@windriver.com>
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Dongdong Deng authored
The kgdb_disable_hw_debug() was an architecture specific function for disabling all hardware breakpoints on a per cpu basis when entering the debug core. This patch will remove the weak function kdbg_disable_hw_debug() and change it into a call back which lives with the rest of hw breakpoint call backs in struct kgdb_arch. Signed-off-by:
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Rabin Vincent authored
DBG_MAX_REG_NUM incorrectly had the number of indices in the GDB regs array rather than the number of registers, leading to an oops when the "rd" command is used in KDB. Cc: stable@kernel.org Signed-off-by:
Rabin Vincent <rabin@rab.in> Signed-off-by:
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Wu Zhangjin authored
Selects HAVE_C_RECORDMCOUNT to use the C version of the recordmcount intead of the old Perl Version of recordmcount. Signed-off-by:
Wu Zhangjin <wuzhangjin@gmail.com> LKML-Reference: <bb99009a9ac79d3f55a8c8bf1c8bd2bc0e1f160e.1288176026.git.wuzhangjin@gmail.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
The TASK_SIZE macro should reflect the size of a user process virtual address space. Previously for 64-bit kernels, this was not the case. The immediate cause of pain was in hugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes trying to mmap a huge page would be served a page with an address outside of the 32-bit address range. But there are other uses of TASK_SIZE in the kernel as well that would like an accurate value. The new definition is nice because it now makes TASK_SIZE and TASK_SIZE_OF() yield the same value for any given process. For 32-bit kernels there should be no change, although I did factor out some code in asm/processor.h that became identical for the 32-bit and 64-bit cases. __UA_LIMIT is now set to ~((1 << SEGBITS) - 1) for 64-bit kernels. This should eliminate the possibility of getting a AddressErrorException in the kernel for addresses that pass the access_ok() test. With the patch applied, I can still run o32, n32 and n64 processes, and have an o32 shell fork/exec both n32 and n64 processes. Signed-off-by:
David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1701/
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Kevin Cernekee authored
Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by:Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
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Kevin Cernekee authored
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates that the L2 cache is disabled and therefore Linux should not attempt to use it. [Ralf: Moved the code added by Kevin's original patch into a separate function that can easily be replaced for platforms that need more a different probe.] Signed-off-by:
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Kevin Cernekee authored
Signed-off-by:
Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by:
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Kevin Cernekee authored
[v2: add "VIPER" marketing name for BMIPS4350] Add processor feature definitions for BMIPS3300, BMIPS4350, BMIPS4380, and BMIPS5000. Signed-off-by:
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Kevin Cernekee authored
BMIPS processor cores are used in 50+ different chipsets spread across 5+ product lines. In many cases the chipsets do not share the same peripheral register layouts, the same register blocks, the same interrupt controllers, the same memory maps, or much of anything else. But, across radically different SoCs that share nothing more than the same BMIPS CPU, a few things are still mostly constant: SMP operations Access to performance counters DMA cache coherency quirks Cache and memory bus configuration So, it makes sense to treat each BMIPS processor type as a generic "building block," rather than tying it to a specific SoC. This makes it easier to support a large number of BMIPS-based chipsets without unnecessary duplication of code, and provides the infrastructure needed to support BMIPS-proprietary features. Signed-off-by:
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Dengcheng Zhu authored
This patch adds the mipsxx Perf-events support based on the skeleton. Generic hardware events and cache events are now fully implemented for the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as R10000/SB1), the generic hardware event tables and cache event tables need to be filled out. To support other CPUs which have different PMU than mipsxx, such as RM9000 and LOONGSON2, the additional files perf_event_$cpu.c need to be created. Raw event is an important part of Perf-events. It helps the user collect performance data for events that are not listed as the generic hardware events and cache events but ARE supported by the CPU's PMU. This patch also adds this feature for mipsxx 24K/34K/74K/1004K. For how to use it, please refer to processor core software user's manual and the comments for mipsxx_pmu_map_raw_event() for more details. Please note that this is a "precise" implementation, which means the kernel will check whether the requested raw events are supported by this CPU and which hardware counters can be assigned for them. To test the functionality of Perf-event, you may want to compile the tool "perf" for your MIPS platform. You can refer to the following URL: http://www.linux-mips.org/archives/linux-mips/2010-10/msg00126.html You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile for your libs, includes, etc. In case you encounter the boot failure in SMVP kernel on multi-threading CPUs, you may take a look at: http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1689/ Signed-off-by:
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Dengcheng Zhu authored
Adds callchain support for MIPS Perf-events. For more info on this feature, please refer to tools/perf/Documentation/perf-report.txt and tools/perf/design.txt. Currently userspace callchain data is not recorded, because we do not have a safe way to do this. Signed-off-by:
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Dengcheng Zhu authored
This patch provides the skeleton of the HW perf event support. To enable this feature, we can not choose the SMTC kernel; Oprofile should be disabled; kernel performance events be selected. Then we can enable it in Kernel type menu. Oprofile for MIPS platforms initializes irq at arch init time. Currently we do not change this logic to allow PMU reservation. If a platform has EIC, we can use the irq base and perf counter irq offset defines for the interrupt controller in specific init_hw_perf_events(). Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely, mipsxx/loongson2/rm9000, can be supported by adding corresponding lower level C files at the bottom. The suggested names of these files are perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for example, we can do this by adding "#include perf_event_mipsxx.c" at the bottom of perf_event.c. In addition, PMUs with 64bit counters are also considered in this patch. Signed-off-by:
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Dengcheng Zhu authored
Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by:
Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by:
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Dengcheng Zhu authored
Perf-events is now using local_t helper functions internally. There is a use of local_xchg(). On MIPS, this is defined to xchg_local() which is missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h to atomic_long_xchg(). Then Perf-events can pass the build. Signed-off-by:
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Florian Fainelli authored
Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost completely identical to AR7 except on a few points: - a second bank of gpios is available - vlynq0 on titan is vlynq1 on ar7 - different PHY addresses for cpmac0 This SoC can be found on commercial products like the Linksys WRTP54G Original patch by Xin with improvments by Florian. Signed-off-by:
Xin Zhen <xlonestar2000@aim.com> Signed-off-by:
Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1563/ Signed-off-by:
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Florian Fainelli authored
In order to detect the Titan variant, we must initialize GPIOs earlier since detection relies on some GPIO values to be set. Signed-off-by:
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David Daney authored
Declare that OCTEON reference boards have both OHCI and EHCI. Add platform devices for the corresponding hardware. Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by:
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David Daney authored
The EHCI and OHCI blocks connection to the I/O bus is controlled by these registers. Signed-off-by:
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David Daney authored
The CN63XXP1 needs a couple of workarounds to ensure memory is not written in unexpected ways. All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We pass a flag to the assembler to cover compiler generated code, and patch uasm for the dynamically generated code. The write buffer threshold is reduced to 4. Signed-off-by:
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David Daney authored
The I2C and UARTS are clocked by the I/O clock, use its rate for these devices. Signed-off-by:
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David Daney authored
Starting with cn63xx Octeon I/O blocks are clocked at a different rate than the CPU. Add a new function octeon_get_io_clock_rate() that yields the I/O clock rate. Also rearrange octeon_get_clock_rate() to get the value from the saved sysinfo structure. Signed-off-by:
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David Daney authored
We can run with any simulator clock rate. Get rid of the code overriding it to 6MHz. Signed-off-by:
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David Daney authored
The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must be scaled by the clock frequency ratio. Signed-off-by:
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David Daney authored
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David Daney authored
The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by:
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David Daney authored
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David Daney authored
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