Commits · 98fd25e7eaa65e2365b8a883d6a572657f9a80e1 · jan.koester / Linux · GitLab

Jun 21, 2015
- devicetree: document Ingenic SoC UART binding · 98fd25e7
  Paul Burton authored May 24, 2015
  98fd25e7
- MIPS: JZ4740: only detect RAM size if not specified in DT · 6ec127fb
  Paul Burton authored May 24, 2015
  6ec127fb
- MIPS: JZ4740: remove clock.h · 1237496a
  Paul Burton authored May 24, 2015
  1237496a
- clk: ingenic: add JZ4780 CGU support · 29136ad5
  Paul Burton authored May 24, 2015
  29136ad5
- MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu · 50d893ff
  Paul Burton authored May 24, 2015
  50d893ff
- MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu · ed286ca5
  Paul Burton authored May 24, 2015
  ed286ca5
- MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu · 41dd641e
  Paul Burton authored May 24, 2015
  41dd641e
- MIPS,clk: migrate JZ4740 to common clock framework · ff1930c6
  Paul Burton authored May 24, 2015
  ff1930c6
- clk: ingenic: add driver for Ingenic SoC CGU clocks · b066303f
  Paul Burton authored May 24, 2015
  b066303f
- DEVICETREE: Add Ingenic CGU binding documentation · fe4ef45b
  Paul Burton authored May 24, 2015
  fe4ef45b
- MIPS: JZ4740: replace use of jz4740_clock_bdata · e06b86a3
  Paul Burton authored May 24, 2015
  e06b86a3
- MIPS: JZ4740: Call jz4740_clock_init earlier · 1f4b8409
  Paul Burton authored May 24, 2015
  1f4b8409
- MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip · 44e08e70
  Paul Burton authored May 24, 2015
  44e08e70
- MIPS: JZ4740: support newer SoC interrupt controllers · 24ccfa06
  Paul Burton authored May 24, 2015
  24ccfa06
- MIPS: JZ4740: Avoid JZ4740-specific naming · 2da01884
  Paul Burton authored May 24, 2015
  2da01884
- MIPS: JZ4740: read intc base address from DT · 3aa94590
  Paul Burton authored May 24, 2015
  3aa94590
- MIPS: JZ4740: define IRQ numbers based on number of intc IRQs · ad68f8d3
  Paul Burton authored May 24, 2015
  ad68f8d3
- MIPS: JZ4740: support >32 interrupts · 943d69c6
  Paul Burton authored May 24, 2015
  943d69c6
- MIPS: JZ4740: Remove jz_intc_base global · fe778ece
  Paul Burton authored May 24, 2015
  fe778ece
- MIPS: JZ4740: drop intc debugfs code · 2aabd281
  Paul Burton authored May 24, 2015
  2aabd281
- MIPS: JZ4740: register an irq_domain for the interrupt controller · 638c8851
  Paul Burton authored May 24, 2015
  638c8851
- MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT · 69ce4b22
  Paul Burton authored May 24, 2015
  69ce4b22
- MIPS: JZ4740: probe interrupt controller via DT · adbdce77
  Paul Burton authored May 24, 2015
  adbdce77
- devicetree: document Ingenic SoC interrupt controller binding · 5f408ebf
  Paul Burton authored May 24, 2015
  5f408ebf
- MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c · 0e81db8f
  Paul Burton authored May 24, 2015
  0e81db8f
- MIPS: JZ4740: use generic plat_irq_dispatch · 2974a356
  Paul Burton authored May 24, 2015
  2974a356
- MIPS: JZ4740: probe CPU interrupt controller via DT · 8e8261eb
  Paul Burton authored May 24, 2015
  8e8261eb
- IRQCHIP: irq_cpu: declare irqchip table entry · 892b8cf0
  Paul Burton authored May 24, 2015
  892b8cf0
- MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip. · 67e38cf2
  Ralf Baechle authored May 26, 2015
  67e38cf2
- MIPS: JZ4740: require & include DT · ffb1843d
  Paul Burton authored May 24, 2015
  ffb1843d
- MIPS: ingenic: Add newer vendor IDs · 252617a4
  Paul Burton authored May 24, 2015
  252617a4
- MIPS: JZ4740: introduce CONFIG_MACH_INGENIC · de361e8b
  Paul Burton authored May 24, 2015
  de361e8b
- devicetree/bindings: add Qi Hardware vendor prefix · 2d06fe53
  Paul Burton authored May 24, 2015
  2d06fe53
- devicetree/bindings: add Ingenic Semiconductor vendor prefix · f289cc7b
  Paul Burton authored May 24, 2015
  f289cc7b
- MIPS: DEC: Update CPU overrides · bc4f12e6
  Maciej W. Rozycki authored May 27, 2015
  bc4f12e6
- MIPS: netlogic: remove unnecessary MTD partition probe specification · cc23cafe
  Brian Norris authored May 18, 2015
  cc23cafe
- MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation · 9a20b092
  Maciej W. Rozycki authored May 27, 2015
  9a20b092
- MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init' · 3bcb03f3
  Maciej W. Rozycki authored May 27, 2015
  3bcb03f3
- MIPS: tlb-r3k: Also invalidate wired TLB entries on boot · dbfbf60f
  Maciej W. Rozycki authored May 27, 2015
  dbfbf60f
- MIPS: dump_tlb: Take XPA into account · 24ca1d98
  James Hogan authored May 19, 2015
  24ca1d98