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  1. Aug 19, 2021
    • Sergey Shtylyov's avatar
      i2c: iop3xx: fix deferred probing · a1299505
      Sergey Shtylyov authored
      
      
      When adding the code to handle platform_get_irq*() errors in the commit
      48944738 ("handle errors returned by platform_get_irq*()"), the
      actual error code was enforced to be -ENXIO in the driver for some
      strange reason.  This didn't matter much until the deferred probing was
      introduced -- which requires an actual error code to be propagated
      upstream from the failure site.
      
      While fixing this, also stop overriding the errors from request_irq() to
      -EIO (done since the pre-git era).
      
      Fixes: 48944738 ("[PATCH] handle errors returned by platform_get_irq*()")
      Signed-off-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
      a1299505
  2. Aug 17, 2021
  3. Aug 11, 2021
  4. Aug 10, 2021
  5. Aug 03, 2021
    • Sergey Shtylyov's avatar
      i2c: highlander: add IRQ check · f16a3bb6
      Sergey Shtylyov authored
      
      
      The driver is written as if platform_get_irq() returns 0 on errors (while
      actually it returns a negative error code), blithely passing these error
      codes to request_irq() (which takes *unsigned* IRQ #) -- which fails with
      -EINVAL. Add the necessary error check to the pre-existing *if* statement
      forcing the driver into the polling mode...
      
      Fixes: 4ad48e6a ("i2c: Renesas Highlander FPGA SMBus support")
      Signed-off-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
      f16a3bb6
  6. Jul 28, 2021
    • Heiner Kallweit's avatar
      i2c: i801: Fix handling SMBHSTCNT_PEC_EN · a6b8bb6a
      Heiner Kallweit authored
      
      
      Bit SMBHSTCNT_PEC_EN is used only if software calculates the CRC and
      uses register SMBPEC. This is not supported by the driver, it supports
      hw-calculation of CRC only (using bit SMBAUXSTS_CRCE). The chip spec
      states the following, therefore never set bit SMBHSTCNT_PEC_EN.
      
      Chapter SMBus CRC Generation and Checking
      If the AAC bit is set in the Auxiliary Control register, the PCH
      automatically calculates and drives CRC at the end of the transmitted
      packet for write cycles, and will check the CRC for read cycles. It will
      not transmit the contents of the PEC register for CRC. The PEC bit must
      not be set in the Host Control register. If this bit is set, unspecified
      behavior will result.
      
      This patch is based solely on the specification and compile-tested only,
      because I have no PEC-capable devices.
      
      Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
      Tested-by: default avatarJean Delvare <jdelvare@suse.de>
      Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
      a6b8bb6a
  7. Jul 25, 2021
  8. Jul 24, 2021
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