Commits · abe7e32f1d50392fbfb6391f4fe1a9f1348b24f3 · jan.koester / Linux · GitLab

Dec 21, 2020
- Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and... · abe7e32f
  Stephen Boyd authored Dec 20, 2020
  abe7e32f
- Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next · b53a1603
  Stephen Boyd authored Dec 20, 2020
  b53a1603
- Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-summary' into clk-next · 699eda28
  Stephen Boyd authored Dec 20, 2020
  699eda28
- Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and... · d240d4c2
  Stephen Boyd authored Dec 20, 2020
  d240d4c2
- Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas'... · 23cae54f
  Stephen Boyd authored Dec 20, 2020
  23cae54f
Dec 20, 2020
- dt-binding: clock: Document canaan,k210-clk bindings · 0c797d2c
  Damien Le Moal authored Dec 20, 2020
  0c797d2c
- dt-bindings: Add Canaan vendor prefix · 6c5c1600
  Damien Le Moal authored Dec 20, 2020
  6c5c1600
- clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" · 4b003f5f
  Geert Uytterhoeven authored Dec 18, 2020
  4b003f5f
- clk: ingenic: Fix divider calculation with div tables · 11a163f2
  Paul Cercueil authored Dec 12, 2020
  11a163f2
Dec 19, 2020
- clk: sunxi-ng: Make sure divider tables have sentinel · 48f68de0
  Jernej Skrabec authored Dec 02, 2020
  48f68de0
- clk: s2mps11: Fix a resource leak in error handling paths in the probe function · d2d94fc5
  Christophe JAILLET authored Dec 12, 2020
  d2d94fc5
- clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 · 6f37689c
  Terry Zhou authored Nov 06, 2020
  6f37689c
- clk: si5351: Wait for bit clear after PLL reset · 5142cbce
  Sascha Hauer authored Nov 30, 2020
  5142cbce
- clk: at91: sam9x60: remove atmel,osc-bypass support · 01324f9e
  Alexandre Belloni authored Dec 02, 2020
  01324f9e
- clk: at91: sama7g5: register cpu clock · 91f3bf0d
  Claudiu Beznea authored Nov 19, 2020
  91f3bf0d
- clk: at91: clk-master: re-factor master clock · 7a110b91
  Claudiu Beznea authored Nov 19, 2020
  7a110b91
- clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz · 120d5d8b
  Claudiu Beznea authored Nov 19, 2020
  120d5d8b
- clk: at91: sama7g5: decrease lower limit for MCK0 rate · f803858a
  Claudiu Beznea authored Nov 19, 2020
  f803858a
- clk: at91: sama7g5: remove mck0 from parent list of other clocks · 4011f03e
  Claudiu Beznea authored Nov 19, 2020
  4011f03e
- clk: at91: clk-sam9x60-pll: allow runtime changes for pll · 8dc4af8b
  Claudiu Beznea authored Nov 19, 2020
  8dc4af8b
- clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics · 0bb4623f
  Eugen Hristev authored Nov 19, 2020
  0bb4623f
- clk: at91: clk-master: add 5th divisor for mck master · e26b3006
  Eugen Hristev authored Nov 19, 2020
  e26b3006
- clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT · 83d00287
  Eugen Hristev authored Nov 19, 2020
  83d00287
- dt-bindings: clock: at91: add sama7g5 pll defines · 3d86ee17
  Eugen Hristev authored Nov 19, 2020
  3d86ee17
- clk: at91: sama7g5: fix compilation error · 91274497
  Claudiu Beznea authored Nov 19, 2020
  91274497
- clk: bcm: dvp: Add MODULE_DEVICE_TABLE() · be439cc4
  Nicolas Saenz Julienne authored Dec 02, 2020
  be439cc4
- clk: bcm: dvp: drop a variable that is assigned to only · c82cf051
  Uwe Kleine-König authored Nov 20, 2020
  c82cf051
Dec 17, 2020
- clk: Trace clk_set_rate() "range" functions · 03813d9b
  Maxime Ripard authored Dec 07, 2020
  03813d9b
- clk: axi-clkgen: move the OF table at the bottom of the file · 16214f97
  Alexandru Ardelean authored Dec 03, 2020
  16214f97
- clk: axi-clkgen: wrap limits in a struct and keep copy on the state object · ac1ee86a
  Alexandru Ardelean authored Dec 03, 2020
  ac1ee86a
- dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format · bd91abb2
  Alexandru Ardelean authored Oct 13, 2020
  bd91abb2
- clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs · 66cc7af3
  David Shah authored Dec 06, 2020
  66cc7af3
- clk: ti: Fix memleak in ti_fapll_synth_setup · 8c6239f6
  Zhang Qilong authored Nov 13, 2020
  8c6239f6
- clk: Add hardware-enable column to clk summary · bf6d43d7
  Dmitry Osipenko authored Nov 15, 2020
  bf6d43d7
- clk: mediatek: Make mtk_clk_register_mux() a static function · 2aeff9d8
  Weiyi Lu authored Nov 13, 2020
  2aeff9d8
Dec 16, 2020
- clk: sifive: Add clock enable and disable ops · 732374a0
  Pragnesh Patel authored Dec 09, 2020
  732374a0
- clk: sifive: Fix the wrong bit field shift · 263ac390
  Zong Li authored Dec 09, 2020
  263ac390
- clk: sifive: Add a driver for the SiFive FU740 PRCI IP block · efc91ae4
  Zong Li authored Dec 09, 2020
  efc91ae4
- clk: sifive: Use common name for prci configuration · 28108fc8
  Zong Li authored Dec 09, 2020
  28108fc8
- clk: sifive: Extract prci core to common base · c816e1dd
  Zong Li authored Dec 09, 2020
  c816e1dd