- Sep 05, 2005
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Kumar Gala authored
Support for the K2 board is no longer maintained and thus being removed Signed-off-by:
Kumar Gala <kumar.gala@freescale.com> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Kumar Gala authored
Support for the CEDAR board no longer exists, removing the defconfig for it Signed-off-by:
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Kumar Gala authored
Support for the BEECH board is no longer maintained and thus being removed Signed-off-by:
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Kumar Gala authored
Support for the ASH board is no longer maintained and thus being removed Signed-off-by:
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Kumar Gala authored
Support for the ADIR board is no longer maintained and thus being removed Signed-off-by:
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Adrian Bunk authored
This #define is only used on sparc. Signed-off-by:
Adrian Bunk <bunk@stusta.de> Signed-off-by:
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Kenneth W Chen authored
I don't think we need to call hugetlb_clean_stale_pgtable() anymore in 2.6.13 because of the rework with free_pgtables(). It now collect all the pte page at the time of munmap. It used to only collect page table pages when entire one pgd can be freed and left with staled pte pages. Not anymore with 2.6.13. This function will never be called and We should turn it into a BUG_ON. I also spotted two problems here, not Adam's fault :-) (1) in huge_pte_alloc(), it looks like a bug to me that pud is not checked before calling pmd_alloc() (2) in hugetlb_clean_stale_pgtable(), it also missed a call to pmd_free_tlb. I think a tlb flush is required to flush the mapping for the page table itself when we clear out the pmd pointing to a pte page. However, since hugetlb_clean_stale_pgtable() is never called, so it won't trigger the bug. Signed-off-by:Ken Chen <kenneth.w.chen@intel.com> Cc: Adam Litke <agl@us.ibm.com> Signed-off-by:
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Adam Litke authored
For demand faulting, we cannot assume that the page tables will be populated. Do what the rest of the architectures do and test p?d_present() while walking down the page table. Signed-off-by:
Adam Litke <agl@us.ibm.com> Cc: <linux-mm@kvack.org> Signed-off-by:
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Adam Litke authored
Initial Post (Wed, 17 Aug 2005) This patch moves the if (! pte_none(*pte)) hugetlb_clean_stale_pgtable(pte); logic into huge_pte_alloc() so all of its callers can be immune to the bug described by Kenneth Chen at http://lkml.org/lkml/2004/6/16/246 > It turns out there is a bug in hugetlb_prefault(): with 3 level page table, > huge_pte_alloc() might return a pmd that points to a PTE page. It happens > if the virtual address for hugetlb mmap is recycled from previously used > normal page mmap. free_pgtables() might not scrub the pmd entry on > munmap and hugetlb_prefault skips on any pmd presence regardless what type > it is. Unless I am missing something, it seems more correct to place the check inside huge_pte_alloc() to prevent a the same bug wherever a huge pte is allocated. It also allows checking for this condition when lazily faulting huge pages later in the series. Signed-off-by:
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Bob Picco authored
With cleanups from Dave Hansen <haveblue@us.ibm.com> SPARSEMEM_EXTREME makes mem_section a one dimensional array of pointers to mem_sections. This two level layout scheme is able to achieve smaller memory requirements for SPARSEMEM with the tradeoff of an additional shift and load when fetching the memory section. The current SPARSEMEM implementation is a one dimensional array of mem_sections which is the default SPARSEMEM configuration. The patch attempts isolates the implementation details of the physical layout of the sparsemem section array. SPARSEMEM_EXTREME requires bootmem to be functioning at the time of memory_present() calls. This is not always feasible, so architectures which do not need it may allocate everything statically by using SPARSEMEM_STATIC. Signed-off-by:
Andy Whitcroft <apw@shadowen.org> Signed-off-by:
Bob Picco <bob.picco@hp.com> Signed-off-by:
Dave Hansen <haveblue@us.ibm.com> Signed-off-by:
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Bob Picco authored
A new option for SPARSEMEM is ARCH_SPARSEMEM_EXTREME. Architecture platforms with a very sparse physical address space would likely want to select this option. For those architecture platforms that don't select the option, the code generated is equivalent to SPARSEMEM currently in -mm. I'll be posting a patch on ia64 ml which uses this new SPARSEMEM feature. ARCH_SPARSEMEM_EXTREME makes mem_section a one dimensional array of pointers to mem_sections. This two level layout scheme is able to achieve smaller memory requirements for SPARSEMEM with the tradeoff of an additional shift and load when fetching the memory section. The current SPARSEMEM -mm implementation is a one dimensional array of mem_sections which is the default SPARSEMEM configuration. The patch attempts isolates the implementation details of the physical layout of the sparsemem section array. ARCH_SPARSEMEM_EXTREME depends on 64BIT and is by default boolean false. I've boot tested under aim load ia64 configured for ARCH_SPARSEMEM_EXTREME. I've also boot tested a 4 way Opteron machine with !ARCH_SPARSEMEM_EXTREME and tested with aim. Signed-off-by:
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- Sep 02, 2005
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Miles Bader authored
Signed-off-by:
Miles Bader <miles@gnu.org> Signed-off-by:
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Miles Bader authored
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Miles Bader authored
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Greg Ungerer authored
Updated defconfig for m68knommu arch. Patch originaly submitted by Jan Dittmer <jdittmer@ppp0.net> Signed-off-by:
Greg Ungerer <gerg@uclinux.com> Signed-off-by:
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Greg Ungerer authored
. add support for the M5235EVB board . add support for the SOM5282 board . add support for the MOD5272 board . fix end of memory define for eLITE board Signed-off-by:
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Greg Ungerer authored
Use the THREAD_SIZE define when manipulating the stack instead of hard coded values (for the 68328 and 68360 sub-architectures). Signed-off-by:
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Greg Ungerer authored
New architecture and board configuration support for m68knommu. . add 523x ColdFire support . add support for SOM5282 and MOD5272 boards . break up the 527x to be separate 5271 and 5275. There is some subtle differences that (like RAM config) that need to be dealt with . add option to support selecting 4k kernel stack Signed-off-by:
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Greg Ungerer authored
Add support for the 523x ColdFire family of processors Signed-off-by:
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Greg Ungerer authored
Make show_stack() consistent with other architectures. Put the vector string names in the .rodata section. Patch originally submitted by Philippe De Muyter <phdm@macqel.be>. Signed-off-by:
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Greg Ungerer authored
Correctly determine the end of ram for ram setups that do not start at base address of 0. Add support for the MOD5272 board, which doesn not have a ram base of 0. Signed-off-by:
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Greg Ungerer authored
. setup for the new 523x ColdFire family . break up of 527x to be 5271 and 5275 . some white space cleanup Signed-off-by:
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Greg Ungerer authored
Low level initialization code for the 523x ColdFire processor family. Signed-off-by:
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- Sep 01, 2005
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Russell King authored
We weren't explicitly setting the page table bits we desired in user_prot in the protection table, which resulted in the user mappings for v6 CPUs being marked global. Signed-off-by:Russell King <rmk+kernel@arm.linux.org.uk>
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Kumar Gala authored
We run into problems if we blindly enable L2 prefetching without checking that the L2 cache is actually enabled. Additionaly, if we disable the L2 cache we need to ensure that we disable L2 prefetching. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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David Gibson authored
In adjusting the logic for SLB miss for the dynamic hugepage stuff, I messed up the !CONFIG_HUGETLB_PAGE case, failing to set the SLB flags properly. This fixes it. It also streamlines the logic for the HUGETLB_PAGE case (removing a couple of branches) while we're at it. Booted, and roughly tested on POWER5 (with and without HUGETLB_PAGE), iSeries/RS64 (no hugepage available), and G5 (with and without HUGETLB_PAGE). Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
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Russell King authored
No point checking what CPU architecture level we have each time within the loop, so precompute the base PMD flags outside the loop. Signed-off-by: -
Russell King authored
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Nicolas Pitre authored
Patch from Nicolas Pitre Signed-off-by:
Nicolas Pitre <nico@cam.org> Signed-off-by:
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Nicolas Pitre authored
Patch from Nicolas Pitre Signed-off-by:
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Nicolas Pitre authored
Patch from Nicolas Pitre Signed-off-by:
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Nicolas Pitre authored
Patch from Nicolas Pitre The prototype for sys_fadvise64_64() is: long sys_fadvise64_64(int fd, loff_t offset, loff_t len, int advice) The argument list is therefore as follows on legacy ABI: fd: type int (r0) offset: type long long (r1-r2) len: type long long (r3-sp[0]) advice: type int (sp[4]) With EABI this becomes: fd: type int (r0) offset: type long long (r2-r3) len: type long long (sp[0]-sp[4]) advice: type int (sp[8]) Not only do we have ABI differences here, but the EABI version requires one additional word on the syscall stack. To avoid the ABI mismatch and the extra stack space required with EABI this syscall is now defined with a different argument ordering on ARM as follows: long sys_arm_fadvise64_64(int fd, int advice, loff_t offset, loff_t len) This gives us the following ABI independent argument distribution: fd: type int (r0) advice: type int (r1) offset: type long long (r2-r3) len: type long long (sp[0]-sp[4]) Now, since the syscall entry code takes care of 5 registers only by default including the store of r4 to the stack, we need a wrapper to store r5 to the stack as well. Because that wrapper was missing and was always required this means that sys_fadvise64_64 never worked on ARM and therefore we can safely reuse its syscall number for our new sys_arm_fadvise64_64 interface. Signed-off-by:
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- Aug 31, 2005
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Martin Hicks authored
Change sn2-specific calls into generic functions. Without this change the uncached allocator will not work on non-sn2 platforms. Signed-off-by:
Greg Edwards <edwardsg@sgi.com> Signed-off-by:
Martin Hicks <mort@sgi.com> Signed-off-by:
Tony Luck <tony.luck@intel.com>
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Catalin Marinas authored
Patch from Catalin Marinas Minor compilation error fix. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Signed-off-by:
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Steve Longerbeam authored
Patch from Steve Longerbeam Adds an implementation of unaligned LDRD and STRD fixups. Also fixes a bug where do_alignment() would misinterpret and fixup an unaligned LDRD/STRD as LDRH/STRH, causing memory corruption. This is the same as Patch #2867/1, but with minor whitespace and comments changes, plus a check for arch-level >= v5TE before printing ai_dword count in proc_alignment_read(). Signed-off-by:
Steve Longerbeam <stevel@mwwireless.net> Signed-off-by:
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Ben Dooks authored
Patch from Ben Dooks timer_dyn_reprogram() fails with an OOPS if the configuration for CONFIG_NO_IDLE_HZ is enabled, and the system has no support for it. Signed-off-by:
Ben Dooks <ben-linux@fluff.org> Signed-off-by:
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- Aug 30, 2005
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Marcelo Tosatti authored
The following patch fixes two warnings in arch/ppc/syslib/m8xx_setup.c Signed-off-by:
Marcelo Tosatti <marcelo.tosatti@cyclades.com> Signed-off-by:
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Ivan Kokshaysky authored
I had some time to think about PCI assign issues in 2.6.13-rc series. The major problem here is that we call pci_assign_unassigned_resources() way too early - at subsys_initcall level. Therefore we give no chances to ACPI and PnP routines (called at fs_initcall level) to reserve their respective resources properly, as the comments in drivers/pnp/system.c and drivers/acpi/motherboard.c suggest: /** * Reserve motherboard resources after PCI claim BARs, * but before PCI assign resources for uninitialized PCI devices */ So I moved the pci_assign_unassigned_resources() call to pcibios_assign_resources() (fs_initcall), which should hopefully fix a lot of problems and make PCIBIOS_MIN_IO tweaks unnecessary. Other changes: - remove resource assignment code from pcibios_assign_resources(), since it duplicates pci_assign_unassigned_resources() functionality and actually does nothing in 2.6.13; - modify ROM assignment code as per Ben's suggestion: try to use firmware settings by default (if PCI_ASSIGN_ROMS is not set); - set CARDBUS_IO_SIZE back to 4K as it's a wonderful stress test for various setups. Confirmed by Tero Roponen <teanropo@cc.jyu.fi> (who had problems with the 4kB CardBus IO size previously). Signed-off-by: -
David Gibson authored
The {BEGIN,END}_FTR_SECTION asm macros used in ppc64 to nop out sections of code at runtime cannot be nested. However, we do nest them in hash_low.S. We get away with it there, because there is nothing between the BEGIN markers for each section. However, that's confusing to someone reading the code. This patch removes the nested ifset and ifclr feature sections, replacing them with a single feature section in the full mask/value form. Signed-off-by:David Gibson <dwg@au1.ibm.com> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Joel Schopp authored
This patch fixes a rare memory leak found by Coverity. Signed-off-by:
Joel Schopp <jschopp@austin.ibm.com> Signed-off-by:
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