According to Documentation/devicetree/bindings/net/fsl-fec.txt the polarity
of "phy-reset-gpios" is assumed to be active-low unless a separate property
"phy-reset-active-high" is available. So replace the inconsistent polarity
description to make the correct active-low reset behavior more obvious.

Signed-off-by: Soeren Moch <smoch@web.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

This commit adds support for Rev. B of a Zodiac Inflight Innovations
development board, mainly intended for DSA and ARINC 429 development
work.

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add missing reg properties to AIPS bus and Cortex-A5's PMU unit.
This change avoids the following warnings:
 Warning (unit_address_vs_reg): Node /soc/aips-bus@40000000 has a unit
 name, but no reg property
 Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000 has a unit
 name, but no reg property
 Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000/pmu@40089000
 has a unit name, but no reg property

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The NAND flash memory populated on Colibri VF61 allows faster NAND
timings than the flash memory on VF50. Additionally, due to divider
limitations, VF61 did clock the flash even slower than VF50. Assign
the NFC clock in the module specific device trees vf500-colibri.dtsi
and vf610-colibri.dtsi respectively.

This increases raw read speed on Colibri VF61 by about 20%.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The Vybrid based Colibri modules provide a on-module PHY which is
connected to the second FEC instance FEC1. Since the on-module
Ethernet port is considered as primary ethernet interface, alias
fec1 as ethernet0. This also makes sure that the first MAC address
provided by the boot loader gets assigned to the FEC instance used
for the on-module PHY.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Introduce imx6sx-sdb-sai.dts so that it is possible to use the
SAI interface.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Property 'dma-source' is not used anywhere, nor it is documented, so
let's just get rid of it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

According to sdma_peripheral_type in include/linux/platform_data/dma-imx.h
IMX_DMATYPE_SAI corresponds to index 24, so fix it accordingly.

Suggested-by: Zidan Wang <zidan.wang@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

pwm2 is provided on the BA16 Q7 module, but is not used on any
of the current configurations. However, future platforms may
utilize this device, so we are simply disabling the node rather
than removing it completely.

Signed-off-by: Justin Waters <justin.waters@timeys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Based on i.MX6 SoloX with 1GB of RAM.

https://boundarydevices.com/product/nit6_solox-imx6/



Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

It is preferred to use the panel compatible string rather than passing the
LCD timings in the device tree.

So pass the "hannstar,hsd100pxn1" compatible string to describe
the LVDS panel on this board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

This baseboard can be used with all TX6 SoMs, but only a certain set
of combinations can be ordered by default. Add support for these
combinations in mainline, so that users can easily adopt their own
combination of SoM and baseboard themselves.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add support for the following i.MX6 based modules from Ka-Ro
electronics GmbH:
TX6S-8034:
Processor    Freescale i.MX 6 Solo, 800MHz
RAM          256MiB DDR3 SDRAM
ROM          128MiB NAND Flash
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  industrial grade (-40°C/-25°C to 105°C Tj)

TX6S-8035:
Processor    Freescale i.MX 6 Solo, 800MHz
RAM          512MiB DDR3 SDRAM
ROM          4GiB eMMC
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  industrial grade (-40°C/-25°C to 105°C Tj)

TX6U-8033:
Processor    Freescale i.MX 6 Dual Lite, 800MHz
RAM          1GiB DDR3 SDRAM
ROM          4GiB eMMC
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  industrial grade (-40°C/-25°C to 105°C Tj)

TX6Q-1036:
Processor    Freescale i.MX 6Quad, 1GHz
RAM          1GB DDR3 SDRAM 64-bit
ROM          8GiB eMMC
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  Extended Consumer Grade (-20°C to 105°C Tj)

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add missing pinctrl for the RTS/CTS lines to uart1 and set the
fsl,uart-has-rtscts property on all UARTs to enable support for HW
handshake.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Move the pinctrl setting for the board LED from the hoggrp node
to a separate node referenced by the LED driver, so that the pin is
free to be used for different purpose when the LED driver is disabled.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

DT maintainers don't like the 'simple-bus' container around the
regulator nodes. So remove it.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Based on i.MX6 Quad Plus with 4GB of RAM.

https://boundarydevices.com/product/nitrogen6max/



Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add mdio node and an appropriate PHY configuration to enable use of
the PHY interrupt for link status changes.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Remove the function node around the pinctrl nodes that was obsoleted
by commit 5fcdf6a7 ("pinctrl: imx: Allow parsing DT without
function nodes"), we can save this container node.

Also move the iomux node to the bottom of the file to improve
readability of the file.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The spidev driver doesn't like to be instantiated via a naked 'spidev'
compatible, though it is very convenient to invoke it this way without
a dedicated SPI device for basic functional testing.
Disable the spi node by default to silence the WARN_ON() from the
spidev driver, but leave the configuration intact otherwise.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add an empty line between properties and subnode in the clocks node.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

GPLv2-only devicetrees make reuse difficult for software components
licensed under a different license.

The consensus is that a GPL/X11 dual-license should allow all necessary
uses, so relicense the imx6*-tx6* files to this combination.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

With SION set the level on such a pin is reported to the UART. So for
example when the CS5 pin is configured for GPIO mode and the level
changes this triggers an RTS interrupt on uart5.

Adding some severity to this issue: The imx uart driver currently
doesn't handle correctly irqs for changes on RI and DCD which are
enabled automatically when the respective UART is driven in DTE mode
(that is, has the fsl,dte-mode property set in the device tree). This
results in a stuck machine because the irq isn't cleared and so stalls
the CPU.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Apart from a few additions this also contains two fixes where the daisy
chain input selection register was missing. Moreover dropped _MUX from
some pins for consistency.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Utilize the new PCIe Tx configuration to properly support the correct
values.

Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The TXUL-0010/-0011 modules are Computers On Module manufactured by
  Ka-Ro electronics GmbH with the following characteristics:
  Processor    Freescale i.MX 6UltraLite MCIMX6G2, 528 MHz
  RAM          256MB 16-bit DDR3 SDRAM
  ROM          128MB NAND Flash (TXUL-0010) / 4GB eMMC (TXUL-0011)
  Power supply Single 3.3 to 5V
  Size         26mm SO-DIMM
  Temp. Range  -40°C to 85°C

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

If enabling the hsmci regulator on card detection, the board can reboot
on sd card insertion. Keeping the regulator always enabled fixes this
issue.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Fixes: 8d545f32 ("ARM: at91/dt: sama5d4 xplained: add regulators for v(q)mmc1 supplies")
Cc: stable@vger.kernel.org #4.3 and later
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

If enabling the hsmci regulator on card detection, the board can reboot
on sd card insertion. Keeping the regulator always enabled fixes this
issue.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Fixes: 1b53e341 ("ARM: at91/dt: sama5d3 xplained: add fixed regulator for vmmc0")
Cc: stable@vger.kernel.org #4.3 and later
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

This will be needed for UniPhier PH1-LD11 and PH1-LD20 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Just for consistent coding style.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Initial commit for PH1-Pro4 Sanji board support.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Initial commit for PH1-Pro4 Ace board support.

Note:
There are two variants for the amount of DDR memory; 1GB or 2GB.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This is used for on-board inter-connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This board has an EEPROM (STMicroelectronics M24C64-WMN6TP) connected
to the I2C channel 0 of the SoC.  Its slave address is 0x54.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This property is used in common by several boards.  Move it to the
common place (uniphier-support-card.dtsi).  If necessary, each board
can still override the property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This patch adds the emac device node for rk3036 SoCs.
We need to let mac clock under the DPLL which is able to provide
the accurate 50MHz what mac_ref need, since that will cause some
unstable things if the cpufreq is working.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>

Allow Openblock AX3 using hardware buffer management with mvneta.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>