Commits · d3d88716a6ce892d3a1fd90d602dded36830ca8d · jan.koester / Linux · GitLab

May 25, 2022
- Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and 'clk-imx' into clk-next · d3d88716
  Stephen Boyd authored May 25, 2022
  d3d88716
- Merge branches 'clk-ti', 'clk-cleanup', 'clk-airoha', 'clk-i2c-simple' and... · 2c29798c
  Stephen Boyd authored May 25, 2022
  2c29798c
May 21, 2022
- clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc() · b7fa6242
  Christophe JAILLET authored May 20, 2022
  b7fa6242
- clk: ti: clkctrl: replace usage of found with dedicated list iterator variable · 560a3164
  Jakob Koschel authored Mar 24, 2022
  560a3164
- clk: ti: composite: Prefer kcalloc over open coded arithmetic · 37004db2
  Len Baker authored Sep 04, 2021
  37004db2
May 19, 2022
- clk: mediatek: mt8173: Switch to clk_hw provider APIs · 5876ee75
  Chen-Yu Tsai authored May 19, 2022
  5876ee75
- clk: mediatek: Switch to clk_hw provider APIs · 6f691a58
  Chen-Yu Tsai authored May 19, 2022
  6f691a58
- clk: mediatek: Replace 'struct clk' with 'struct clk_hw' · 609cc5e1
  Chen-Yu Tsai authored May 19, 2022
  609cc5e1
- clk: mediatek: apmixed: Drop error message from clk_register() failure · 012715ad
  Chen-Yu Tsai authored May 19, 2022
  012715ad
- clk: mediatek: Make mtk_clk_register_composite() static · f247c17d
  Chen-Yu Tsai authored May 19, 2022
  f247c17d
- clk: mediatek: use en_mask as a pure div_en_mask · e1fd35f5
  Chun-Jie Chen authored May 13, 2022
  e1fd35f5
- clk: mediatek: update compatible string for MT7986 ethsys · 544e9ec7
  Sam Shih authored May 09, 2022
  544e9ec7
May 18, 2022
- clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base() · bea0b66e
  Hangyu Hua authored May 18, 2022
  bea0b66e
May 17, 2022
- Merge tag 'clk-imx-5.19' of... · 3972b152
  Stephen Boyd authored May 17, 2022
  3972b152
- clk: imx8mp: fix usb_root_clk parent · cf7f3f4f
  Peng Fan authored May 07, 2022
  cf7f3f4f
- Merge tag 'sunxi-clk-for-5.19-1' of... · 0594058b
  Stephen Boyd authored May 16, 2022
  0594058b
- Merge tag 'for-5.19-clk' of... · 8b9d9e9f
  Stephen Boyd authored May 16, 2022
  8b9d9e9f
- Merge tag 'renesas-clk-for-v5.19-tag2' of... · 13982e86
  Stephen Boyd authored May 16, 2022
  13982e86
- clk: fixed-rate: Remove redundant if statement · b69b0adc
  Li Zhengyu authored May 09, 2022
  b69b0adc
May 06, 2022
- clk: sunxi-ng: h616: Add PLL derived 32KHz clock · 31ab5169
  Andre Przywara authored Apr 29, 2022
  31ab5169
- clk: sunxi-ng: h6-r: Add RTC gate clock · 38d321b6
  Andre Przywara authored Apr 29, 2022
  38d321b6
- clk: tegra: Update kerneldoc to match prototypes · 6f6baf69
  Thierry Reding authored May 06, 2022
  6f6baf69
- clk: renesas: r9a09g011: Add eth clock and reset entries · 23426d1b
  Phil Edworthy authored May 04, 2022
  23426d1b
- clk: renesas: Add RZ/V2M support using the rzg2l driver · 1dd65bb0
  Phil Edworthy authored May 03, 2022
  1dd65bb0
May 05, 2022
- clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg · 8090bea3
  Phil Edworthy authored May 03, 2022
  8090bea3
- clk: renesas: rzg2l: Make use of CLK_MON registers optional · 63804400
  Phil Edworthy authored May 03, 2022
  63804400
- clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers · 75b0ad42
  Phil Edworthy authored May 03, 2022
  75b0ad42
- clk: renesas: rzg2l: Add read only versions of the clk macros · 8282fe00
  Phil Edworthy authored May 03, 2022
  8282fe00
- clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro · ceb3bfab
  Phil Edworthy authored May 03, 2022
  ceb3bfab
- dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC · 4a526957
  Phil Edworthy authored May 03, 2022
  4a526957
- Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19 · 049bddcb
  Geert Uytterhoeven authored May 05, 2022
  049bddcb
- clk: renesas: r9a07g044: Fix OSTM1 module clock name · 53c58c08
  Geert Uytterhoeven authored May 02, 2022
  53c58c08
- clk: renesas: r9a07g043: Add clock and reset entries for ADC · 84c9829d
  Biju Das authored May 01, 2022
  84c9829d
- clk: renesas: r9a07g043: Add TSU clock and reset entry · b6768530
  Biju Das authored May 01, 2022
  b6768530
- clk: renesas: r9a07g043: Add RSPI clock and reset entries · 14d8857d
  Biju Das authored May 01, 2022
  14d8857d
- clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller · 4e683604
  Biju Das authored May 01, 2022
  4e683604
- clk: renesas: r9a07g044: Add DSI clock and reset entries · 67f80edf
  Biju Das authored Apr 30, 2022
  67f80edf
- clk: renesas: r9a07g044: Add LCDC clock and reset entries · 6f6178f1
  Biju Das authored Apr 30, 2022
  6f6178f1
- clk: renesas: r9a07g044: Add M4 Clock support · 31d5ef2f
  Biju Das authored Apr 30, 2022
  31d5ef2f
- clk: renesas: r9a07g044: Add M3 Clock support · 359f10c1
  Biju Das authored Apr 30, 2022
  359f10c1