- Jun 17, 2013
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Shawn Guo authored
Add SoC level device tree source for imx6sl. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Dirk Behme authored
Configure the data and tag latency for the L2 cache. This improves the system performance. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] which does writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); In this patch we are doing the same via the device tree. Signed-off-by:
Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
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Huang Shijie authored
Since the SPI/NOR has pin conflict with the WEIM NOR, we disable the spi/nor by default. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Huang Shijie authored
The SPI/NOR needs this gpio for CS. So add this gpio in the hog pinctrl. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Huang Shijie authored
The SPI/NOR needs this gpio for CS. So add this gpio in the hog pinctrl. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Huang Shijie authored
Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Huang Shijie authored
enable the gpmi-nand for imx6q-sabreauto and imx6qdl-sabreauto boards. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Huang Shijie authored
add the pinctrl item for gpmi-nand. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Huang Shijie authored
The gpmi does not use the MX6Q_PAD_NANDF_CS2__NAND_CE2_B and MX6Q_PAD_NANDF_CS3__NAND_CE3_B. Just remove them. Signed-off-by:
Huang Shijie <b32955@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Alexander Shiyan authored
Added SPI node and PMIC MC13783 (spi0.0) to imx27-phytec-phycore DT file. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Alexander Shiyan authored
Add aliases to determine the proper SPI bus number. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
This adds support for the Ka-Ro TX53 System-On-Module. As a baseboard is needed to operate it, only a *.dtsi and no Makefile entry. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add a group to the uart2 pinctrl. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add a group to the uart1 pinctrl. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add pinctrl for pwm2. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add a group to the ecspi pinctrl. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add a group to the csi pinctrl. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steffen Trumtrar authored
Add a group to the audmux pinctrl. Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds support for the DENX M53EVK board. The board currently supports NAND, Ethernet, UART, CAN, I2C. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
With device tree clk lookup support in place, we can move audio codec clk lookup for ssi_ext1 into device tree now, so that imx53_qsb_init() can be saved. Since ssi_ext2 lookup is used nowhere, it gets removed together with ssi_ext1 lookup from clk driver. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinctrl data for PWM1 on MX53. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinmux for IPU LCD 1 and IPU LVDS. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinctrl data for NAND on MX53. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinctrl data for different mux of I2C2 on MX53. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinctrl data for different mux of I2C1 on MX53. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinctrl data for different mux of CAN1 on MX53. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
This patch adds pinctrl data for the AUDMUX4 on MX53. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Philipp Zabel authored
This allows to order the i2c character devices correctly, so that /dev/i2c-0 corresponds to i2c1, /dev/i2c-1 corresponds to i2c2, and so on. Currently they are ordered by register address. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Gwenhael Goavec-Merou authored
Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Michael Grzeschik authored
Signed-off-by:
Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Michael Grzeschik authored
Signed-off-by:
Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Michael Grzeschik authored
Signed-off-by:
Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Michael Grzeschik authored
Signed-off-by:
Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- Jun 06, 2013
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Thomas Petazzoni authored
The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Jun 05, 2013
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Marc C authored
The previous mask values for the legacy ARM CPU IDs were conflicting with the CPU ID assignments for late-generation CPUs (like the Qualcomm MSM/QSD or Broadcom Brahma-15 processors). This change corrects the legacy ARM CPU ID value so that the jump table can fall-through to the appropriate cache maintenance / MMU functions. Signed-off-by:
Marc C <marc.ceeeee@gmail.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Arnd Bergmann authored
In August 2012, Matthew Gretton-Dann checked a change into binutils labelled "Error on obsolete & warn on deprecated registers", apparently as part of ARMv8 support. Apparently, this was supposed to emit the message "Warning: This coprocessor register access is deprecated in ARMv8" when using certain mcr/mrc instructions and building for ARMv8. Unfortunately, the message that is actually emitted appears to be '(null)', which is less helpful in comparison. Even more unfortunately, this is biting us on every single kernel build with a new gas, because arch/arm/boot/compressed/head.S and some other files in that directory are built with -march=all since kernel commit 80cec14a "[ARM] Add -march=all to assembly file build in arch/arm/boot/compressed" back in v2.6.28. This patch reverts Russell's nice solution and instead marks the head.S file to be built for armv7-a, which fortunately lets us build all instructions in that file without warnings even on the broken binutils. Without this patch, building anything results in: arch/arm/boot/compressed/head.S: Assembler messages: arch/arm/boot/compressed/head.S:565: Warning: (null) arch/arm/boot/compressed/head.S:676: Warning: (null) arch/arm/boot/compressed/head.S:698: Warning: (null) arch/arm/boot/compressed/head.S:722: Warning: (null) arch/arm/boot/compressed/head.S:726: Warning: (null) arch/arm/boot/compressed/head.S:957: Warning: (null) arch/arm/boot/compressed/head.S:996: Warning: (null) arch/arm/boot/compressed/head.S:997: Warning: (null) arch/arm/boot/compressed/head.S:1027: Warning: (null) arch/arm/boot/compressed/head.S:1035: Warning: (null) arch/arm/boot/compressed/head.S:1046: Warning: (null) arch/arm/boot/compressed/head.S:1060: Warning: (null) arch/arm/boot/compressed/head.S:1092: Warning: (null) arch/arm/boot/compressed/head.S:1094: Warning: (null) arch/arm/boot/compressed/head.S:1095: Warning: (null) arch/arm/boot/compressed/head.S:1102: Warning: (null) arch/arm/boot/compressed/head.S:1134: Warning: (null) Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org Cc: Matthew Gretton-Dann <matthew.gretton-dann@arm.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Nicolas Pitre authored
Selecting this option produces: AS arch/arm/boot/compressed/debug.o arch/arm/boot/compressed/debug.S:4:33: fatal error: mach/debug-macro.S: No such file or directory compilation terminated. make[3]: *** [arch/arm/boot/compressed/debug.o] Error 1 The semihosting support cannot be modelled into a senduart macro as it requires memory space for argument passing. So the CONFIG_DEBUG_LL_INCLUDE may not have any sensible value and the include directive should be omitted. While at it, let's add proper semihosting output support to the decompressor. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- Jun 03, 2013
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Suman Anna authored
OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM. The PWM capability property is missing from the node definitions of couple of timers. Add ti,timer-pwm attribute for timer 5, 6, 8 and 11. Signed-off-by:
Suman Anna <s-anna@ti.com> [benoit.cousson@linaro.org: Update changelog and subject to highlight the fix] Signed-off-by:
Benoit Cousson <benoit.cousson@linaro.org>
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Kevin Hilman authored
Earlier commits ensured proper muxing of pins related to proper TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC). However these only fixed legacy boot and not DT boot. For DT boot, the default mux values need to be set properly in DT. Special thanks to Nishanth Menon for the review and catching some major flaws in earlier versions. Tested on OMAP4430/Panda and OMAP4460/Panda-ES. Cc: Nishanth Menon <nm@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by:
Kevin Hilman <khilman@linaro.org> Acked-by:
Grygorii Strashko <grygorii.strashko@ti.com> [benoit.cousson@linaro.org: Slightly change the subject to align board name with file name] Signed-off-by:
Benoit Cousson <benoit.cousson@linaro.org>
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Lars Poeschel authored
The gpmc driver is actually looking for "gpmc,num-cs" and "gpmc,num-waitpins" properties in DT. The binding doc also states this. Correct the properties in the dts to provide the right values for the gpmc driver. Signed-off-by:
Lars Poeschel <poeschel@lemonage.de> Acked-by:
Peter Korsgaard <jacmet@sunsite.dk> Acked-by:
Pekon Gupta <pekon@ti.com> Signed-off-by:
Benoit Cousson <benoit.cousson@linaro.org>
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