- Jun 21, 2006
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Jon Loeliger authored
Signed-off-by:
Jeff Brown <Jeff.Brown@freescale.com> Signed-off-by:
Xianghua Xiao <x.xiao@freescale.com> Signed-off-by:
Jon Loeliger <jdl@freescale.com> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- Jun 15, 2006
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Dave C Boutcher authored
Currently the kernel blindly halts all the processors and calls the ibm,suspend-me rtas call. If the firmware is not in the correct state, we then re-start all the processors and return. It is much smarter to first check the firmware state, and only if it is waiting, call the ibm,suspend-me call. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
On non partitioned machines we currently set the HV bit in kernel space only. It turns out we are supposed to maintain the HV bit in both user and kernel space. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
Allocate IOMMU tables local to the relevant node. Signed-off-by:
Anton Blanchard <anton@samba.org> Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
of_node_to_nid returns -1 if the associativity cannot be found. This means pcibus_to_cpumask has to be careful not to pass a negative index into node_to_cpumask. Since pcibus_to_node could be used a lot, and of_node_to_nid is slow (it walks a list doing strcmps), lets also cache the node in the pci_controller struct. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
Remove some stale POWER3/POWER4/970 on 32bit kernel support. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
Forthcoming machines will extend the FPSCR to 64 bits. We already had a 64-bit save area for the FPSCR, but we need to use a new form of the mtfsf instruction. Fortunately this new form is decoded as an ordinary mtfsf by existing 64-bit processors. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Jake Moilanen authored
Instead of trying to make PPC64 MSI fit in a Intel-centric MSI layer, a simple short-term solution is to hook the pci_{en/dis}able_msi() calls and make a machdep call. The rest of the MSI functions are superfluous for what is needed at this time. Many of which can have machdep calls added as needed. Ben and Michael Ellerman are looking into rewrite the MSI layer to be more generic. However, in the meantime this works as a interim solution. Signed-off-by:
Jake Moilanen <moilanen@austin.ibm.com> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
Some POWER5+ machines can do 64k hardware pages for normal memory but not for cache-inhibited pages. This patch lets us use 64k hardware pages for most user processes on such machines (assuming the kernel has been configured with CONFIG_PPC_64K_PAGES=y). User processes start out using 64k pages and get switched to 4k pages if they use any non-cacheable mappings. With this, we use 64k pages for the vmalloc region and 4k pages for the imalloc region. If anything creates a non-cacheable mapping in the vmalloc region, the vmalloc region will get switched to 4k pages. I don't know of any driver other than the DRM that would do this, though, and these machines don't have AGP. When a region gets switched from 64k pages to 4k pages, we do not have to clear out all the 64k HPTEs from the hash table immediately. We use the _PAGE_COMBO bit in the Linux PTE to indicate whether the page was hashed in as a 64k page or a set of 4k pages. If hash_page is trying to insert a 4k page for a Linux PTE and it sees that it has already been inserted as a 64k page, it first invalidates the 64k HPTE before inserting the 4k HPTE. The hash invalidation routines also use the _PAGE_COMBO bit, to determine whether to look for a 64k HPTE or a set of 4k HPTEs to remove. With those two changes, we can tolerate a mix of 4k and 64k HPTEs in the hash table, and they will all get removed when the address space is torn down. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- Jun 12, 2006
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Paul Mackerras authored
The pgdir field in the paca was a leftover from the dynamic VSIDs patch, and is not used in the current kernel code. This removes it. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- Jun 11, 2006
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akpm@osdl.org authored
Fix build error when CONFIG_ACPI not defined Signed-off-by:
Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de>
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Paul Mackerras authored
This adds a vdso_base element to the mm_context_t for 32-bit compiles (both for ARCH=powerpc and ARCH=ppc). This fixes the compile errors that have been reported in arch/powerpc/kernel/signal_32.c. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- Jun 10, 2006
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Markus Lidel authored
From: Markus Lidel <Markus.Lidel@shadowconnect.com> - Fixed locking of struct i2o_exec_wait in Executive-OSM - Removed LCT Notify in i2o_exec_probe() which caused freeing memory and accessing freed memory during first enumeration of I2O devices - Added missing locking in i2o_exec_lct_notify() - removed put_device() of I2O controller in i2o_iop_remove() which caused the controller structure get freed to early - Fixed size of mempool in i2o_iop_alloc() - Fixed access to freed memory in i2o_msg_get() See http://bugzilla.kernel.org/show_bug.cgi?id=6561 Signed-off-by:
Markus Lidel <Markus.Lidel@shadowconnect.com> Cc: <stable@kernel.org> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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- Jun 09, 2006
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Paul Mackerras authored
This gives the ability to control whether alignment exceptions get fixed up or reported to the process as a SIGBUS, using the existing PR_SET_UNALIGN and PR_GET_UNALIGN prctls. We do not implement the option of logging a message on alignment exceptions. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Anton Blanchard authored
This new prctl is intended for changing the execution mode of the processor, on processors that support both a little-endian mode and a big-endian mode. It is intended for use by programs such as instruction set emulators (for example an x86 emulator on PowerPC), which may find it convenient to use the processor in an alternate endianness mode when executing translated instructions. Note that this does not imply the existence of a fully-fledged ABI for both endiannesses, or of compatibility code for converting system calls done in the non-native endianness mode. The program is expected to arrange for all of its system call arguments to be presented in the native endianness. Switching between big and little-endian mode will require some care in constructing the instruction sequence for the switch. Generally the instructions up to the instruction that invokes the prctl system call will have to be in the old endianness, and subsequent instructions will have to be in the new endianness. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Michael Neuling authored
POWER6 moves some of the MMCRA bits and also requires some bits to be cleared each PMU interrupt. Signed-off-by:
Michael Neuling <mikey@neuling.org> Acked-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Christoph Hellwig authored
Make sure dma_alloc_coherent allocates memory from the local node. This is important on Cell where we avoid going through the slow cpu interconnect. Note: I could only test this patch on Cell, it should be verified on some pseries machine by those that have the hardware. Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Christoph Hellwig authored
On 64bit powerpc we can find out what node a pci bus hangs off, so implement the topology.h macros that export this information. For 32bit this seems a little more difficult, but I don't know of 32bit powerpc NUMA machines either, so let's leave it out for now. Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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John Rose authored
This patch attempts to handle RTAS "busy" return codes in a more simple and consistent manner. Typical callers of RTAS shouldn't have to manage wait times and delay calls. This patch also changes the kernel to use msleep() rather than udelay() when a runtime delay is necessary. This will avoid CPU soft lockups for extended delay conditions. Signed-off-by:
John Rose <johnrose@austin.ibm.com> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Benjamin Herrenschmidt authored
Our MMU hash management code would not set the "C" bit (changed bit) in the hardware PTE when updating a RO PTE into a RW PTE. That would cause the hardware to possibly to a write back to the hash table to set it on the first store access, which in addition to being a performance issue, might also hit a bug when running with native hash management (non-HV) as our code is specifically optimized for the case where no write back happens. Thus there is a very small therocial window were a hash PTE can become corrupted if that HPTE has just been upgraded to read write, a store access happens on it, and that races with another processor evicting that same slot. Since eviction (caused by an almost full hash) is extremely rare, the bug is very unlikely to happen fortunately. This fixes by allowing the updating of the protection bits in the native hash handling to also set (but not clear) the "C" bit, and, in order to also improve performances in the general case, by always setting that bit on newly inserted hash PTE so that writeback really never happens. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Benjamin Herrenschmidt authored
This patch cleans up some locking & error handling in the ppc vdso and moves the vdso base pointer from the thread struct to the mm context where it more logically belongs. It brings the powerpc implementation closer to Ingo's new x86 one and also adds an arch_vma_name() function allowing to print [vsdo] in /proc/<pid>/maps if Ingo's x86 vdso patch is also applied. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Renzo Davoli authored
I have tested PPC_PTRACE_GETREGS and PPC_PTRACE_SETREGS on umview. I do not understand why historically these tags has been defined as PPC_PTRACE_GETREGS and PPC_PTRACE_SETREGS instead of simply PTRACE_[GS]ETREGS. The other "originality" is that the address must be put into the "addr" field instead of the "data" field as stated in the manual. Signed-off-by:
renzo davoli <renzo@cs.unibo.it> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- Jun 08, 2006
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Martin Schwidefsky authored
From: Martin Schwidefsky <schwidefsky@de.ibm.com> __futex_atomic_op needs to do an atomic operation in the user address space, not the kernel address space. Add the missing sacf 256/sacf 0 to switch to the secondary mode before doing the compare-and-swap. In addition add another fixup for catch specification exceptions if the compare-and-swap address is not aligned. Signed-off-by:
Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Jens Axboe authored
There's a race between shutting down one io scheduler and firing up the next, in which a new io could enter and cause the io scheduler to be invoked with bad or NULL data. To fix this, we need to maintain the queue lock for a bit longer. Unfortunately we cannot do that, since the elevator init requires to be run without the lock held. This isn't easily fixable, without also changing the mempool API. So split the initialization into two parts, and alloc-init operation and an attach operation. Then we can preallocate the io scheduler and related structures, and run the attach inside the lock after we detach the old one. This patch has survived 30 minutes of 1 second io scheduler switching with a very busy io load. Signed-off-by:
Jens Axboe <axboe@suse.de> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Ralf Baechle authored
From: Ralf Baechle <ralf@linux-mips.org> <linux/mempolicy.h> uses struct mm_struct and relies on a definition or declaration somehow magically being dragged in which may result in a build: [...] CC mm/mempolicy.o In file included from mm/mempolicy.c:69: include/linux/mempolicy.h:150: warning: âstruct mm_structâ declared inside parameter list include/linux/mempolicy.h:150: warning: its scope is only this definition or declaration, which is probably not what you want include/linux/mempolicy.h:175: warning: âstruct mm_structâ declared inside parameter list mm/mempolicy.c:622: error: conflicting types for âdo_migrate_pagesâ include/linux/mempolicy.h:175: error: previous declaration of âdo_migrate_pagesâ was here mm/mempolicy.c:1661: error: conflicting types for âmpol_rebind_mmâ include/linux/mempolicy.h:150: error: previous declaration of âmpol_rebind_mmâ was here make[1]: *** [mm/mempolicy.o] Error 1 make: *** [mm] Error 2 [ralf@denk linux-ip35]$ Including <linux/sched.h> is a step into direction of include hell so fixed by adding a forward declaration of struct mm_struct instead. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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- Jun 05, 2006
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Chad Reese authored
Move memory_present() in arch/mips/kernel/setup.c. When using sparsemem extreme, this function does an allocate for bootmem. This would always fail since init_bootmem hasn't been called yet. Move memory_present after free_bootmem. This only marks actual memory ranges as present instead of the entire address space. Signed-off-by:
Chad Reese <creese@caviumnetworks.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
RM7000 has 40-bit virtual / 36-bit physical address space. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Sergei Shtylyov authored
Fix the non-linear memory mapping done via remap_file_pages() -- it didn't work on any MIPS CPU because the page offset clashing with _PAGE_FILE and some other page protection bits which should have been left zeros for this kind of pages. Signed-off-by:
Konstantin Baydarov <kbaidarov@ru.mvista.com> Signed-off-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Sergei Shtylyov authored
With 64-bit physical address enabled, 'swapon' was causing kernel oops on Alchemy CPUs (MIPS32) because of the swap entry type field corrupting the _PAGE_FILE bit in 'pte_low' field. So, switch to storing the swap entry in 'pte_high' field using all its bits except _PAGE_GLOBAL and _PAGE_VALID which gives 25 bits for the swap entry offset. Signed-off-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Sergei Shtylyov authored
Fix mprotect() syscall for MIPS32 CPUs with 36-bit physical address support: pte_modify() macro didn't clear the hardware page protection bits before modifying... Signed-off-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
A while ago prom_prepare_cpus was replaced by plat_prepare_cpus but the declaration has stayed unchanged. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Increase alignment of BogoMIPS loop to 8 bytes. Having the delay loop overlap cache line boundaries may cause instable delays. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Al Viro authored
From: Al Viro <viro@zeniv.linux.org.uk> uml __user annotations Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk> Signed-off-by:
Jeff Dike <jdike@addtoit.com> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Jeff Dike authored
From: Jeff Dike <jdike@addtoit.com> Add an empty asm/irqflags.h, which seems to satisfy the lock validator enough that UML builds. Signed-off-by:
Jeff Dike <jdike@addtoit.com> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Andrew Morton authored
From: Andrew Morton <akpm@osdl.org> drivers/rtc/rtc-m48t86.c: In function `m48t86_rtc_read_time': drivers/rtc/rtc-m48t86.c:51: error: structure has no member named `ia64_mv' drivers/rtc/rtc-m48t86.c:55: error: structure has no member named `ia64_mv' drivers/rtc/rtc-m48t86.c:56: error: structure has no member named `ia64_mv' drivers/rtc/rtc-m48t86.c:57: error: structure has no member named `ia64_mv' drivers/rtc/rtc-m48t86.c:58: error: structure has no member named `ia64_mv' drivers/rtc/rtc-m48t86.c:60: error: structure has no member named `ia64_mv' readb() and writeb() are macros on ia64. Cc: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Ivan Kokshaysky authored
From: Ivan Kokshaysky <ink@jurassic.park.msu.ru> After removal of fixup_cpu_present_map() function Alpha ended up with an empty cpu_present_map, so secondary CPUs on SMP systems are not being started. Worse, on some platforms we route interrupts to secondary CPUs using cpu_possible_map which is still populated properly. As a result, these interrupts go nowhere so the machines like DP264 aren't able to boot even with a primary CPU. Fixed basically by s/cpu_present_mask/cpu_present_map/. Thanks to Ernst Herzberg for reporting the bug and testing the fix. Cc: Ernst Herzberg <list-lkml@net4u.de> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Ralf Baechle authored
From: Ralf Baechle <ralf@linux-mips.org> <linux/mmzone.h> uses PAGE_SIZE, PAGE_SHIFT from <asm/page.h> without including that header itself. For some sparsemem configurations this may result in build errors like: CC init/initramfs.o In file included from include/linux/gfp.h:4, from include/linux/slab.h:15, from include/linux/percpu.h:4, from include/linux/rcupdate.h:41, from include/linux/dcache.h:10, from include/linux/fs.h:226, from init/initramfs.c:2: include/linux/mmzone.h:498:22: warning: "PAGE_SHIFT" is not defined In file included from include/linux/gfp.h:4, from include/linux/slab.h:15, from include/linux/percpu.h:4, from include/linux/rcupdate.h:41, from include/linux/dcache.h:10, from include/linux/fs.h:226, from init/initramfs.c:2: include/linux/mmzone.h:526: error: `PAGE_SIZE' undeclared here (not in a function) include/linux/mmzone.h: In function `__pfn_to_section': include/linux/mmzone.h:573: error: `PAGE_SHIFT' undeclared (first use in this function) include/linux/mmzone.h:573: error: (Each undeclared identifier is reported only once include/linux/mmzone.h:573: error: for each function it appears in.) include/linux/mmzone.h: In function `pfn_valid': include/linux/mmzone.h:578: error: `PAGE_SHIFT' undeclared (first use in this function) make[1]: *** [init/initramfs.o] Error 1 make: *** [init] Error 2 Signed-off-by:
Ralf Baechle <ralf@linux-mips.org> Seems-reasonable-to: Andy Whitcroft <apw@shadowen.org> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Peter Oberparleiter authored
From: Peter Oberparleiter <peter.oberparleiter@de.ibm.com> The path grouping can fail due to non-unique pathgroup-IDs. The source for the CPU-ID part of the ID was incorrectly specified on 64 bit systems. Additionally, the length of the ID was too large due to incorrect data packing declaration. Fix CPU-ID lowcore address and add missing packing declaration. Signed-off-by:
Peter Oberparleiter <peter.oberparleiter@de.ibm.com> Signed-off-by:
Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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