- Dec 08, 2006
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David Howells authored
This facility provides three entry points: ilog2() Log base 2 of unsigned long ilog2_u32() Log base 2 of u32 ilog2_u64() Log base 2 of u64 These facilities can either be used inside functions on dynamic data: int do_something(long q) { ...; y = ilog2(x) ...; } Or can be used to statically initialise global variables with constant values: unsigned n = ilog2(27); When performing static initialisation, the compiler will report "error: initializer element is not constant" if asked to take a log of zero or of something not reducible to a constant. They treat negative numbers as unsigned. When not dealing with a constant, they fall back to using fls() which permits them to use arch-specific log calculation instructions - such as BSR on x86/x86_64 or SCAN on FRV - if available. [akpm@osdl.org: MMC fix] Signed-off-by:David Howells <dhowells@redhat.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: David Howells <dhowells@redhat.com> Cc: Wojtek Kaniewski <wojtekka@toxygen.net> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Josef Sipek authored
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Josef Sipek <jsipek@fsl.cs.sunysb.edu> Signed-off-by:
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef Sipek authored
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Josef "Jeff" Sipek authored
Change all the uses of f_{dentry,vfsmnt} to f_path.{dentry,mnt} in the x86_64 arch code. Signed-off-by:Josef "Jeff" Sipek <jsipek@cs.sunysb.edu> Signed-off-by:
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Josef "Jeff" Sipek authored
Change all the uses of f_{dentry,vfsmnt} to f_path.{dentry,mnt} in the i386 arch code. Signed-off-by: -
Judith Lebzelter authored
Switch ppc over to using the generic BUG implementation. Signed-off-by:
Judith Lebzelter <judith@osdl.org> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Jeff Dike authored
The BUG changes in -mm3 need some arch support. This patch adds the UML support needed. For the most part, it was stolen from the underlying architecture. The exception is the kernel eip < PAGE_OFFSET test, which is wrong for skas mode UMLs. Signed-off-by:
Jeff Dike <jdike@addtoit.com> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by:
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Jeremy Fitzhardinge authored
This makes x86-64 use the generic BUG machinery. The main advantage in using the generic BUG machinery for x86-64 is that the inlined overhead of BUG is just the ud2a instruction; the file+line information are no longer inlined into the instruction stream. This reduces cache pollution. Signed-off-by:
Jeremy Fitzhardinge <jeremy@goop.org> Cc: Andi Kleen <ak@muc.de> Cc: Hugh Dickens <hugh@veritas.com> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by:
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Jeremy Fitzhardinge authored
This makes i386 use the generic BUG machinery. There are no functional changes from the old i386 implementation. The main advantage in using the generic BUG machinery for i386 is that the inlined overhead of BUG is just the ud2a instruction; the file+line(+function) information are no longer inlined into the instruction stream. This reduces cache pollution, and makes disassembly work properly. Signed-off-by:
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Peter Zijlstra authored
Fix the locking of signal->tty. Use ->sighand->siglock to protect ->signal->tty; this lock is already used by most other members of ->signal/->sighand. And unless we are 'current' or the tasklist_lock is held we need ->siglock to access ->signal anyway. (NOTE: sys_unshare() is broken wrt ->sighand locking rules) Note that tty_mutex is held over tty destruction, so while holding tty_mutex any tty pointer remains valid. Otherwise the lifetime of ttys are governed by their open file handles. This leaves some holes for tty access from signal->tty (or any other non file related tty access). It solves the tty SLAB scribbles we were seeing. (NOTE: the change from group_send_sig_info to __group_send_sig_info needs to be examined by someone familiar with the security framework, I think it is safe given the SEND_SIG_PRIV from other __group_send_sig_info invocations) [schwidefsky@de.ibm.com: 3270 fix] [akpm@osdl.org: various post-viro fixes] Signed-off-by:Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by:
Alan Cox <alan@redhat.com> Cc: Oleg Nesterov <oleg@tv-sign.ru> Cc: Prarit Bhargava <prarit@redhat.com> Cc: Chris Wright <chrisw@sous-sol.org> Cc: Roland McGrath <roland@redhat.com> Cc: Stephen Smalley <sds@tycho.nsa.gov> Cc: James Morris <jmorris@namei.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jeff Dike <jdike@addtoit.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Jan Kara <jack@ucw.cz> Signed-off-by:
Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by:
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Hirokazu Takata authored
This patch supports "m32r-g00ff" bootloader for an OPSPUT platform. Applying this patch, it is possible to do ATA-boot from an IDE drive or HTTP-boot from network by m32r-g00ff. * arch/m32r/boot/compressed/m32r_sio.c: Fix hangup on OPSPUT at boot. * arch/m32r/kernel/io_opsput.c: IDE support for OPSPUT. * arch/m32r/kernel/setup_opsput.c: ditto. * include/asm-m32r/ide.h: ditto. Signed-off-by:Kazuhiro Inaoka <inaoka@linux-m32r.org> Signed-off-by:
Hirokazu Takata <takata@linux-m32r.org> Signed-off-by:
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Hirokazu Takata authored
Don't mask the lower 12-bit of the page fault address. In the current m32r kernel implementation, we use an access exception to detect page faults. This patch fixes ace_handler (access exception handler) for m32r. In order to check userspace address in do_page_fault, we have to pass full 32-bit address to do_page_fault. Signed-off-by:
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Hirokazu Takata authored
The m32r kernel 2.6.18-rc1 or after cause build errors of "unknown isa configuration" for userspace application programs, such as glibc, gdb, etc. This is because the recent kernel do not include linux/config.h not to expose kernel headers for userspace. To fix the above compile errors, this patch fixes two headers ptrace.h and sigcontext.h for m32r and makes them platform-independent. Signed-off-by:
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- Dec 07, 2006
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Ben Dooks authored
Do not bother masking/unmasking the parent IRQ for the mulitplexed EINT irqs, as masking the leaf seems to be fine. Signed-off-by:
Ben Dooks <ben-linux@fluff.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Nicolas Pitre authored
It appears that include/asm-arm/bug.h requires include/linux/stddef.h for the definition of NULL. It seems that stddef.h was always included indirectly in most cases, and that issue was properly fixed a while ago. Then commit 5047f09b incorrectly reverted change from commit ff10952a (bad dwmw2) and the problem recently resurfaced. Because the third argument to __bug() is never used anyway, RMK suggested getting rid of it entirely instead of readding #include <linux/stddef.h> which this patch does. Signed-off-by:
Nicolas Pitre <nico@cam.org> Signed-off-by:
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Ben Dooks authored
Add the mapping for the third S3C2440 serial port into the default serial devices for the Osiris. Signed-off-by:
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Ben Dooks authored
The RX3715 is similar to the H1940 in the way that suspend to RAM works, so we can use most of the extant support for the H1940 with only a few modifictions Signed-off-by:
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Ben Dooks authored
Support for the GPIO attached LEDs on the VR1000 Signed-off-by:
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Yan Burman authored
Replace kmalloc+memset with kzalloc Signed-off-by:
Yan Burman <burman.yan@gmail.com> Signed-off-by:
Tony Luck <tony.luck@intel.com>
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Christoph Lameter authored
There is a name clash with ia64 arch code in Andrew's tree. Rename is_avialable_memory() to is_memory_available() to avoid the clash. Signed-off-by:
Christoph Lameter <clameter@sgi.com> Signed-off-by:
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Tony Luck authored
Now we have our own highly optimized assembly code version of this routine (Thanks Ken!) we should export it so that it can be used. Signed-off-by: -
Venkatesh Pallipadi authored
PAL_GET_PSTATE accepts a type argument to return different kinds of frequency information. Refer: Intel Itanium®Architecture Software Developer's Manual - Volume 2: System Architecture, Revision 2.2 (http://developer.intel.com/design/itanium/manuals/245318.htm ) Add the support for type argument and use Instantaneous frequency in the acpi driver. Also fix a bug, where in return value of PAL_GET_PSTATE was getting compared with 'control' bits instead of 'status' bits. Signed-off-by:
Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by:
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Kenneth W Chen authored
While working on implementing csum_ipv6_magic, I noticed that current version of ip_fast_csum will potentially return bits above "unsigned short" as 1. While no harm is done right now because all call sites will chop off the upper bits when it uses the return value. However, this is still dangerous and buggy. Here is a patch to enforce that the function really returns unsigned short in the native register format. The fix is free as there are plenty open slot to add one more asm instruction. Signed-off-by:
Ken Chen <kenneth.w.chen@intel.com> Signed-off-by:
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Kenneth W Chen authored
The asm version is 4.4 times faster than the generic C version and 10X smaller in code size. Signed-off-by:
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Russ Anderson authored
Additional updates to conform with Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006). Add pal_bus_features_s bits 52 & 53 (page 2:347) Add pal_vm_info_2_s field max_purges (page 2:2:451) Add PAL_GET_HW_POLICY call (page 2:381) Add PAL_SET_HW_POLICY call (page 2:439) Sample output before: --------------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/vm_info Physical Address Space : 50 bits Virtual Address Space : 61 bits Protection Key Registers(PKR) : 16 Implemented bits in PKR.key : 24 Hash Tag ID : 0x2 Size of RR.rid : 24 Supported memory attributes : WB, UC, UCE, WC, NaTPage --------------------------------------------------------------------- Sample output after: --------------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/vm_info Physical Address Space : 50 bits Virtual Address Space : 61 bits Protection Key Registers(PKR) : 16 Implemented bits in PKR.key : 24 Hash Tag ID : 0x2 Max Purges : 1 Size of RR.rid : 24 Supported memory attributes : WB, UC, UCE, WC, NaTPage --------------------------------------------------------------------- Signed-off-by:
Russ Anderson <(rja@sgi.com)> Signed-off-by:
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Russ Anderson authored
Add the printing of additional processor features to proc_features. Based on Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006) fields (pages 2:430-2:432). This patch gets the features back in sync with the spec. Sample output before: -------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/processor_info XIP,XPSR,XFS implemented : On NoCtrl XR1-XR3 implemented : On NoCtrl Disable dynamic predicate prediction : NotImpl Disable processor physical number : NotImpl Disable dynamic data cache prefetch : NotImpl Disable dynamic inst cache prefetch : NotImpl Disable dynamic branch prediction : NotImpl Disable BINIT on processor time-out : On Ctrl Disable dynamic power management (DPM) : NotImpl Disable coherency : NotImpl Disable cache : NotImpl Enable CMCI promotion : Off Ctrl Enable MCA to BINIT promotion : Off Ctrl Enable MCA promotion : NotImpl Enable BERR promotion : NotImpl cobra:~ # -------------------------------------------------------------- Sample output after: -------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/processor_info Unimplemented instruction address fault : NotImpl INIT, PMI, and LINT pins : NotImpl Simple unimplimented instr addresses : On NoCtrl Variable P-state performance : NotImpl Virtual machine features implemeted : On NoCtrl XIP,XPSR,XFS implemented : On NoCtrl XR1-XR3 implemented : On NoCtrl Disable dynamic predicate prediction : NotImpl Disable processor physical number : NotImpl Disable dynamic data cache prefetch : NotImpl Disable dynamic inst cache prefetch : NotImpl Disable dynamic branch prediction : NotImpl Disable P-states : Off Ctrl Enable MCA on Data Poisoning : Off Ctrl Enable vmsw instruction : On Ctrl Enable extern environmental notification : NotImpl Disable BINIT on processor time-out : On Ctrl Disable dynamic power management (DPM) : NotImpl Disable coherency : NotImpl Disable cache : NotImpl Enable CMCI promotion : Off Ctrl Enable MCA to BINIT promotion : Off Ctrl Enable MCA promotion : NotImpl Enable BERR promotion : NotImpl cobra:~ # -------------------------------------------------------------- Signed-off-by:
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John Keller authored
On Altix systems, the /proc/irq/nn/smp_affinity mask is not being setup at device iniitalization, or updated after an interrupt redirection. This patch resolves those issues. Signed-off-by:
John Keller <jpk@sgi.com> Signed-off-by:
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Matthew Wilcox authored
0/NULL confusion and some missing UL on constants. Signed-off-by:
Matthew Wilcox <matthew@wil.cx> Signed-off-by:
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Zou Nan hai authored
Changes and updates. 1. Remove fake rendz path and related code according to discuss with Khalid Aziz. 2. fc.i offset fix in relocate_kernel.S. 3. iospic shutdown code eoi and mask race fix from Fujitsu. 4. Warm boot hook in machine_kexec to SN SAL code from Jack Steiner. 5. Send slave to SAL slave loop patch from Jay Lan. 6. Kdump on non-recoverable MCA event patch from Jay Lan 7. Use CTL_UNNUMBERED in kdump_on_init sysctl. Signed-off-by:
Zou Nan hai <nanhai.zou@intel.com> Signed-off-by:
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Dan Williams authored
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by:
Dan Williams <dan.j.williams@intel.com> Signed-off-by:
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