- Aug 07, 2013
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Jason Cooper authored
Signed-off-by:Jason Cooper <jason@lakedaemon.net>
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- Aug 06, 2013
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Ezequiel Garcia authored
Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of the ocp node, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. In addition, we encode the PCIe memory and I/O apertures in the MBus node, according to the MBus DT binding specification. The choice made is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for I/O space. These apertures can be changed in each per-board DT file. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by:
Andrew Lunn <andrew@lunn.ch> Tested-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
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Ezequiel Garcia authored
This macro is used to define window's target ID and attribute cells for the MBus ranges entries. Signed-off-by:
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Ezequiel Garcia authored
Add a minimal MBus node, just to allow the MBus driver to probe. Follow-up patches will migrate the rest of the nodes appropriately. Signed-off-by:
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Ezequiel Garcia authored
Signed-off-by:
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Ezequiel Garcia authored
This commit replaces the legacy MBus initialization with the new DT-based in Kirkwood. For boards that are not yet converted to DT, we keep the legacy initialization. Signed-off-by:
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Ezequiel Garcia authored
Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Ezequiel Garcia authored
Now that mbus has been added to the device tree, it's possible to move the DeviceBus out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Signed-off-by:
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Ezequiel Garcia authored
In order to access the SoC BootROM, we need to declare a mapping (through a ranges property). The mbus driver will use this property to allocate a suitable address decoding window. Signed-off-by:
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Ezequiel Garcia authored
The Armada 370/XP SoC family has a completely configurable address space handled by the MBus controller. This patch introduces the device tree layout of MBus, making the 'soc' node as mbus-compatible. Since every peripheral/controller is a child of this 'soc' node, this makes all of them sit behind the mbus, thus describing the hardware accurately. A translation entry has been added for the internal-regs mapping. This can't be done in the common armada-370-xp.dtsi because A370 and AXP have different addressing width. Signed-off-by:
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Ezequiel Garcia authored
Signed-off-by:
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Ezequiel Garcia authored
Now that the mbus device tree binding has been introduced, we can switch over to it. Also, and since the initialization of the mbus driver is quite fundamental for the system to work properly, this patch adds a BUG() in case mbus fails to initialize. Signed-off-by:
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Ezequiel Garcia authored
The address decoding window to access the BootROM should not be allocated programatically, but instead declared in the device tree. Signed-off-by:
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Thomas Petazzoni authored
With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by:
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Thomas Petazzoni authored
With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by:
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Thomas Petazzoni authored
With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by:
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Thomas Petazzoni authored
With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by:
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- Jul 13, 2013
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Al Viro authored
[suggested by Rasmus Villemoes] make O_DIRECTORY | O_RDWR part of O_TMPFILE; that will fail on old kernels in a lot more cases than what I came up with. And make sure O_CREAT doesn't get there... Signed-off-by:Al Viro <viro@zeniv.linux.org.uk>
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Olof Johansson authored
OMAP recently changed how the platforms are configured, so OMAP2/3/4 SoC support is no longer enabled by default. Add them back. Enable new ethernet driver for sunxi. The i.MX console options moved due to resorting, no functional change. Signed-off-by:Olof Johansson <olof@lixom.net>
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- Jul 12, 2013
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Vincent Stehlé authored
- Add i.MX serial console support. This gives us the boot messages on UART on e.g. the i.MX6Q sabre sd platform. - Add the necessary config options, to allow booting with NFS root on an i.MX6 sabre sd. - Add Freescale LPUART serial console support. This gives us the boot messages on UART on e.g. the Vybrid VF610 Tower board. Signed-off-by:
Vincent Stehlé <vincent.stehle@freescale.com> Cc: Russell King <linux@arm.linux.org.uk> [olof: squashed three commits down to one] Signed-off-by:
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Dave Hansen authored
I completely botched understanding the calling conventions of do_div(). I assumed that do_div() returned the result instead of realizing that it modifies its argument and returns a remainder. The side-effect from this would be bogus numbers for the "msecs" value in the warning messages: INFO: NMI handler (perf_event_nmi_handler) took too long to run: 0.114 msecs Note, there was a second fix posted by Stephane Eranian for a separate patch which I also botched: http://lkml.kernel.org/r/20130704223010.GA30625@quad Signed-off-by:
Dave Hansen <dave.hansen@linux.intel.com> Cc: Dave Hansen <dave@sr71.net> Link: http://lkml.kernel.org/r/20130708214404.B0B6EA66@viggo.jf.intel.com Signed-off-by:
Ingo Molnar <mingo@kernel.org>
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- Jul 11, 2013
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Russell King authored
The watchdog infrastructure in Dove is no different from that in Orion5x or Kirkwood, so let's enable it for Dove. The only things missing are a few register settings in Dove's bridge-regs.h. Rather than duplicating the same register bit masks for the RSTOUTn_MASK and BRIDGE_CAUSE registers, move the definitions into the watchdog driver itself. Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> Acked-by:
Wim Van Sebroeck <wim@iguana.be>
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Viresh Kumar authored
Interrupt request doesn't use the right API: The TWD watchdog uses a per-cpu interrupt (usually interrupt #30), and the GIC configuration should flag it as such. With this setup, request_irq() should fail, and the right API is request_percpu_irq(), together with enable_percpu_irq()/disable_percpu_irq(). Nothing ensures the userspace ioctl() will end-up kicking the watchdog on the right CPU. There are no users of this driver since a long time and it makes more sense to get rid of it as nobody is looking to fix it. In case somebody wakes up after this has been removed and needs it, please revert this driver and pick these updates (These were never pushed to mainline): http://comments.gmane.org/gmane.linux.ports.arm.kernel/245998 Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Acked-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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Michel Lespinasse authored
Since all architectures have been converted to use vm_unmapped_area(), there is no remaining use for the free_area_cache. Signed-off-by:
Michel Lespinasse <walken@google.com> Acked-by:
Rik van Riel <riel@redhat.com> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David Howells <dhowells@redhat.com> Cc: Helge Deller <deller@gmx.de> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Eliezer Tamir authored
Rename LL_SO to BUSY_POLL_SO Rename sysctl_net_ll_{read,poll} to sysctl_busy_{read,poll} Fix up users of these variables. Fix documentation for sysctl. a patch for the socket.7 man page will follow separately, because of limitations of my mail setup. Signed-off-by:Eliezer Tamir <eliezer.tamir@linux.intel.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- Jul 10, 2013
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Olivier DANET authored
Commit e4c6bfd2 ("mm: rearrange vm_area_struct for fewer cache misses") changed the layout of the vm_area_struct structure, it broke several SPARC32 assembly routines which used numerical constants for accessing the vm_mm field. This patch defines the VMA_VM_MM constant to replace the immediate values. Signed-off-by:
Olivier DANET <odanet@caramail.com> Signed-off-by:
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Andreas Larsson authored
Even if data snooping is enabled, without separate snoop tags snooping will not work when the MMU is enabled. Signed-off-by:
Andreas Larsson <andreas@gaisler.com> Signed-off-by:
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Chen Gang authored
For the related next strcpy(), the destination length is less than 512, but the source maximize length may be 'OPROMMAXPARAM' (4096) which is more than 512. One work flow may: openprom_sunos_ioctl() -> if (cmd == OPROMSETOPT) getstrings() -> will alloc buffer with size 'OPROMMAXPARAM'. opromsetopt() -> devide the buffer into 'var' and 'value' of_set_property() -> pass prom_setprop() -> pass ldom_set_var() And do not mind the additional 4 alignment buffer increasing, since 'sizeof(pkt) - sizeof(pkt.header)' is 4 alignment at least. Signed-off-by:Chen Gang <gang.chen@asianux.com> Signed-off-by:
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Michal Simek authored
The reason is that other applications like strace think that every __NR_xx is syscall. Also __NR_syscalls is not used by user applications/libs. Signed-off-by:Michal Simek <michal.simek@xilinx.com>
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- Jul 09, 2013
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Jason Liu authored
When the local timer freq changed, the twd_update_frequency function should be run all the CPUs include itself, otherwise, the twd freq will not get updated and the local timer will not run correcttly. smp_call_function will run functions on all other CPUs, but not include himself, this is not correct,use on_each_cpu instead to fix this issue. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Jason Liu <r64343@freescale.com> Signed-off-by:
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Fabio Estevam authored
imx_v6_v7_defconfig handles both multi-core and single-core SoCs, and it has CONFIG_SMP=y selected by default. With such config we cannot select ARM_ERRATA_364296, as it depends on !SMP. Let ARM_ERRATA_364296 be undependent on CONFIG_SMP, so that we can select this erratum for the ARM1136 SoCs, even if CONFIG_SMP=y is enabled. Reviewed-by:
Dave Martin <Dave.Martin@arm.com> Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Helge Deller authored
When running the LTP testsuite one may hit this kernel BUG() with the write06 testcase: kernel BUG at mm/filemap.c:2023! CPU: 1 PID: 8614 Comm: writev01 Not tainted 3.10.0-rc7-64bit-c3000+ #6 IASQ: 0000000000000000 0000000000000000 IAOQ: 00000000401e6e84 00000000401e6e88 IIR: 03ffe01f ISR: 0000000010340000 IOR: 000001fbe0380820 CPU: 1 CR30: 00000000bef80000 CR31: ffffffffffffffff ORIG_R28: 00000000bdc192c0 IAOQ[0]: iov_iter_advance+0x3c/0xc0 IAOQ[1]: iov_iter_advance+0x40/0xc0 RP(r2): generic_file_buffered_write+0x204/0x3f0 Backtrace: [<00000000401e764c>] generic_file_buffered_write+0x204/0x3f0 [<00000000401eab24>] __generic_file_aio_write+0x244/0x448 [<00000000401eadc0>] generic_file_aio_write+0x98/0x150 [<000000004024f460>] do_sync_readv_writev+0xc0/0x130 [<000000004025037c>] compat_do_readv_writev+0x12c/0x340 [<00000000402505f8>] compat_writev+0x68/0xa0 [<0000000040251d88>] compat_SyS_writev+0x98/0xf8 Reason for this crash is a gcc miscompilation in the fault handlers of pa_memcpy() which return the fault address instead of the copied bytes. Since this seems to be a generic problem with gcc-4.7.x (and below), it's better to simplify the fault handlers in pa_memcpy to avoid this problem. Here is a simple reproducer for the problem: int main(int argc, char **argv) { int fd, nbytes; struct iovec wr_iovec[] = { { "TEST STRING ",32}, { (char*)0x40005000,32} }; // random memory. fd = open(DATA_FILE, O_RDWR | O_CREAT, 0666); nbytes = writev(fd, wr_iovec, 2); printf("return value = %d, errno %d (%s)\n", nbytes, errno, strerror(errno)); return 0; } In addition, John David Anglin wrote: There is no gcc PR as pa_memcpy is not legitimate C code. There is an implicit assumption that certain variables will contain correct values when an exception occurs and the code randomly jumps to one of the exception blocks. There is no guarantee of this. If a PR was filed, it would likely be marked as invalid. Signed-off-by:Helge Deller <deller@gmx.de> Signed-off-by:
John David Anglin <dave.anglin@bell.net> Cc: <stable@vger.kernel.org> # 3.8+ Signed-off-by:
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John David Anglin authored
I still see the occasional random segv on rp3440. Looking at one of these (a code 15), it appeared the problem must be with the cache handling of anonymous pages. Reviewing this, I noticed that the space register %sr1 might be being clobbered when we flush an anonymous page. Register %sr1 is used for TLB purges in a couple of places. These purges are needed on PA8800 and PA8900 processors to ensure cache consistency of flushed cache lines. The solution here is simply to move the %sr1 load into the TLB lock region needed to ensure that one purge executes at a time on SMP systems. This was already the case for one use. After a few days of operation, I haven't had a random segv on my rp3440. Signed-off-by:
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Helge Deller authored
If the value which should be moved into a space register is zero, we can optimize the inline assembly to become "mtsp %r0,%srX". Signed-off-by: -
Helge Deller authored
The latest PA-RISC Boot Loader (palo) allows loading of gzip compressed vmlinuz kernels. So let's now switch to build a vmlinuz file when we build a palo boot image. PALO version 1.9 (or higher) is required for this which is available at git://git.kernel.org/pub/scm/linux/kernel/git/deller/palo.git Signed-off-by:
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Helge Deller authored
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Kyungsik Lee authored
Integrates the LZ4 decompression code to the arm pre-boot code. Signed-off-by:
Kyungsik Lee <kyungsik.lee@lge.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Borislav Petkov <bp@alien8.de> Cc: Florian Fainelli <florian@openwrt.org> Cc: Yann Collet <yann.collet.73@gmail.com> Signed-off-by:
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Robin Holt authored
Merge together the unicore32, arm, and x86 reboot= command line parameter handling. Signed-off-by:
Robin Holt <holt@sgi.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Russ Anderson <rja@sgi.com> Cc: Robin Holt <holt@sgi.com> Acked-by:
Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by:
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Robin Holt authored
Preparing to move the parsing of reboot= to generic kernel code forces the change in reboot_mode handling to use the enum. [akpm@linux-foundation.org: fix arch/arm/mach-socfpga/socfpga.c] Signed-off-by:
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Robin Holt authored
Prepare for the moving the parsing of reboot= to the generic kernel code by making reboot_mode into a more generic form. Signed-off-by:
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