Unverified Commit 1bf42cfe authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dts-for-v6.5-tag1' of... 

Merge tag 'renesas-dts-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.5

  - Add partial display support for the RZ/G2L and RZ/V2L SoCs and the
    RZ/G2L{,C} SMARC EVK development boards,
  - Add camera support for the RZ/GV2L SoC and the RZ/V2L and RZ/G2LC
    SMARC EVK development boards,
  - Add Multi-Function Timer Pulse Unit 3 support for the RZ/G2L and
    RZ/V2L SoCs,
  - Add PWM support for the R-Car V3U SoC.

* tag 'renesas-dts-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a779a0: Add PWM nodes
  arm64: dts: renesas: r9a07g054: Add MTU3a node
  arm64: dts: renesas: r9a07g044: Add MTU3a node
  arm64: dts: renesas: rzg2lc-smarc: Enable CRU, CSI support
  arm64: dts: renesas: rzv2l-smarc: Enable CRU, CSI support
  arm64: dts: renesas: r9a07g054: Add CSI and CRU nodes
  arm64: dts: renesas: rzg2lc-smarc: Link DSI with ADV7535
  arm64: dts: renesas: rzg2l-smarc: Link DSI with ADV7535
  arm64: dts: renesas: r9a07g054: Add DSI node
  arm64: dts: renesas: r9a07g044: Add DSI node
  arm64: dts: renesas: r9a07g054: Add vspd node
  arm64: dts: renesas: r9a07g044: Add vspd node
  arm64: dts: renesas: r9a07g054: Add fcpvd node
  arm64: dts: renesas: r9a07g044: Add fcpvd node

Link: https://lore.kernel.org/r/cover.1685094244.git.geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents c4558562 18cbbdd8

arch/arm64/boot/dts/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -79,10 +79,12 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb 
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo



dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb

dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo

dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb

dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo



dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb

dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo



dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb

arch/arm64/boot/dts/renesas/r8a779a0.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -943,6 +943,56 @@ avb5: ethernet@e6850000 { 
			status = "disabled";

		};



		pwm0: pwm@e6e30000 {

			compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";

			reg = <0 0xe6e30000 0 0x10>;

			#pwm-cells = <2>;

			clocks = <&cpg CPG_MOD 628>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 628>;

			status = "disabled";

		};



		pwm1: pwm@e6e31000 {

			compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";

			reg = <0 0xe6e31000 0 0x10>;

			#pwm-cells = <2>;

			clocks = <&cpg CPG_MOD 628>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 628>;

			status = "disabled";

		};



		pwm2: pwm@e6e32000 {

			compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";

			reg = <0 0xe6e32000 0 0x10>;

			#pwm-cells = <2>;

			clocks = <&cpg CPG_MOD 628>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 628>;

			status = "disabled";

		};



		pwm3: pwm@e6e33000 {

			compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";

			reg = <0 0xe6e33000 0 0x10>;

			#pwm-cells = <2>;

			clocks = <&cpg CPG_MOD 628>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 628>;

			status = "disabled";

		};



		pwm4: pwm@e6e34000 {

			compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";

			reg = <0 0xe6e34000 0 0x10>;

			#pwm-cells = <2>;

			clocks = <&cpg CPG_MOD 628>;

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 628>;

			status = "disabled";

		};



		scif0: serial@e6e60000 {

			compatible = "renesas,scif-r8a779a0",

				     "renesas,rcar-gen4-scif", "renesas,scif";

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+123 −0
Original line number Diff line number Diff line
@@ -174,6 +174,76 @@ soc: soc { 
		#size-cells = <2>;

		ranges;



		mtu3: timer@10001200 {

			compatible = "renesas,r9a07g044-mtu3",

				     "renesas,rz-mtu3";

			reg = <0 0x10001200 0 0xb00>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",

					  "tgiv0", "tgie0", "tgif0",

					  "tgia1", "tgib1", "tgiv1", "tgiu1",

					  "tgia2", "tgib2", "tgiv2", "tgiu2",

					  "tgia3", "tgib3", "tgic3", "tgid3",

					  "tgiv3",

					  "tgia4", "tgib4", "tgic4", "tgid4",

					  "tgiv4",

					  "tgiu5", "tgiv5", "tgiw5",

					  "tgia6", "tgib6", "tgic6", "tgid6",

					  "tgiv6",

					  "tgia7", "tgib7", "tgic7", "tgid7",

					  "tgiv7",

					  "tgia8", "tgib8", "tgic8", "tgid8",

					  "tgiv8", "tgiu8";

			clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		ssi0: ssi@10049c00 {

			compatible = "renesas,r9a07g044-ssi",

				     "renesas,rz-ssi";
@@ -697,6 +767,59 @@ csi2cru: endpoint@0 { 
			};

		};



		dsi: dsi@10850000 {

			compatible = "renesas,r9a07g044-mipi-dsi",

				     "renesas,rzg2l-mipi-dsi";

			reg = <0 0x10850000 0 0x20000>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "seq0", "seq1", "vin1", "rcv",

					  "ferr", "ppi", "debug";

			clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,

				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,

				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,

				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,

				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,

				 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;

			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";

			resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,

				 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,

				 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;

			reset-names = "rst", "arst", "prst";

			power-domains = <&cpg>;

			status = "disabled";

		};



		vspd: vsp@10870000 {

			compatible = "renesas,r9a07g044-vsp2";

			reg = <0 0x10870000 0 0x10000>;

			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,

				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,

				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;

			clock-names = "aclk", "pclk", "vclk";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_LCDC_RESET_N>;

			renesas,fcp = <&fcpvd>;

		};



		fcpvd: fcp@10880000 {

			compatible = "renesas,r9a07g044-fcpvd",

				     "renesas,fcpv";

			reg = <0 0x10880000 0 0x10000>;

			clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,

				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,

				 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;

			clock-names = "aclk", "pclk", "vclk";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_LCDC_RESET_N>;

		};



		cpg: clock-controller@11010000 {

			compatible = "renesas,r9a07g044-cpg";

			reg = <0 0x11010000 0 0x10000>;

arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso

0 → 100644
+21 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree overlay for the RZ/G2LC SMARC EVK with

 * OV5645 camera connected to CSI and CRU enabled.

 *

 * Copyright (C) 2023 Renesas Electronics Corp.

 */



/dts-v1/;

/plugin/;



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>



#define OV5645_PARENT_I2C i2c0

#include "rz-smarc-cru-csi-ov5645.dtsi"



&ov5645 {

	enable-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_HIGH>;

	reset-gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>;

};

arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso

+1 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree overlay for the RZ/G2L SMARC EVK with OV5645 camera

 * Device Tree overlay for the RZ/{G2L, V2L} SMARC EVK with OV5645 camera

 * connected to CSI and CRU enabled.

 *

 * Copyright (C) 2023 Renesas Electronics Corp.