Commit 59b4c078 authored by Martin Leung's avatar Martin Leung Committed by Alex Deucher
Browse files

Revert "drm/amd/display: Speed up DML fast_validate path" 



This reverts commit 1b5d0e7e.

It caused corruption in some media players.

Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarMartin Leung <Martin.Leung@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 857aa2be

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+0 −2
Original line number Diff line number Diff line
@@ -1564,7 +1564,6 @@ bool dcn32_internal_validate_bw(struct dc *dc, 
		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

			dm_prefetch_support_fclk_and_stutter;



		context->bw_ctx.dml.validate_max_state = fast_validate;

		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);



		/* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */
@@ -1573,7 +1572,6 @@ bool dcn32_internal_validate_bw(struct dc *dc, 
				dm_prefetch_support_stutter;

			vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

		}

		context->bw_ctx.dml.validate_max_state = false;



		if (vlevel < context->bw_ctx.dml.soc.num_states) {

			memset(split, 0, sizeof(split));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+17 −20
Original line number Diff line number Diff line
@@ -1707,7 +1707,7 @@ static void mode_support_configuration(struct vba_vars_st *v, 
void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)

{

	struct vba_vars_st *v = &mode_lib->vba;

	int i, j, start_state;

	int i, j;

	unsigned int k, m;

	unsigned int MaximumMPCCombine;

	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
@@ -1720,10 +1720,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
#endif



	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/

	if (mode_lib->validate_max_state)

		start_state = v->soc.num_states - 1;

	else

		start_state = 0;



	/*Scale Ratio, taps Support Check*/



	mode_lib->vba.ScaleRatioAndTapsSupport = true;
@@ -2012,7 +2009,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage

			&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;



	for (i = start_state; i < v->soc.num_states; i++) {

	for (i = 0; i < v->soc.num_states; i++) {

		for (j = 0; j < 2; j++) {

			mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;

			mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
@@ -2289,7 +2286,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = start_state; i < v->soc.num_states; ++i) {

	for (i = 0; i < v->soc.num_states; ++i) {

		mode_lib->vba.ExceededMultistreamSlots[i] = false;

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

			if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
@@ -2389,7 +2386,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = start_state; i < v->soc.num_states; ++i) {

	for (i = 0; i < v->soc.num_states; ++i) {

		mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

			if (mode_lib->vba.BlendingAndTiming[k] == k
@@ -2406,7 +2403,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = start_state; i < v->soc.num_states; ++i) {

	for (i = 0; i < v->soc.num_states; ++i) {

		mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;

		mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
@@ -2424,7 +2421,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = start_state; i < v->soc.num_states; i++) {

	for (i = 0; i < v->soc.num_states; i++) {

		mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;

		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

			if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2461,7 +2458,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	/* Check DSC Unit and Slices Support */

	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;



	for (i = start_state; i < v->soc.num_states; ++i) {

	for (i = 0; i < v->soc.num_states; ++i) {

		mode_lib->vba.NotEnoughDSCUnits[i] = false;

		mode_lib->vba.NotEnoughDSCSlices[i] = false;

		v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
@@ -2496,7 +2493,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	}



	/*DSC Delay per state*/

	for (i = start_state; i < v->soc.num_states; ++i) {

	for (i = 0; i < v->soc.num_states; ++i) {

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

			mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(

					mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
@@ -2523,7 +2520,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 


	//Calculate Swath, DET Configuration, DCFCLKDeepSleep

	//

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
@@ -2658,7 +2655,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
			mode_lib->vba.SurfaceSizeInMALL,

			&mode_lib->vba.ExceededMALLSize);



	for (i = start_state; i < v->soc.num_states; i++) {

	for (i = 0; i < v->soc.num_states; i++) {

		for (j = 0; j < 2; j++) {

			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

				mode_lib->vba.swath_width_luma_ub_this_state[k] =
@@ -2885,7 +2882,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	}



	//Calculate Return BW

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

				if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2964,7 +2961,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
			&mode_lib->vba.MinPrefetchMode,

			&mode_lib->vba.MaxPrefetchMode);



	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j)

			mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i];

	}
@@ -3086,7 +3083,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				mode_lib->vba.DCFCLKState);

	} // UseMinimumRequiredDCFCLK == true



	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i,

					mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j],
@@ -3095,7 +3092,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	}



	//Re-ordering Buffer Support Check

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024

					/ mode_lib->vba.ReturnBWPerState[i][j]
@@ -3117,7 +3114,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				+ mode_lib->vba.ReadBandwidthChroma[k];

	}



	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] =

				dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j]
@@ -3141,7 +3138,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 


	/* Prefetch Check */



	for (i = start_state; i < (int) v->soc.num_states; ++i) {

	for (i = 0; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {



			mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h

+0 −1
Original line number Diff line number Diff line
@@ -91,7 +91,6 @@ struct display_mode_lib { 
	struct dal_logger *logger;

	struct dml_funcs funcs;

	struct _vcs_dpi_display_e2e_pipe_params_st dml_pipe_state[6];

	bool validate_max_state;

};



void dml_init_instance(struct display_mode_lib *lib,