ARM: dts: imx6ul-14x14-evk: switch lcdif pixel clock to video pll

By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD
source. If this mux is allowed to propagate rate changes to its parent,
setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD
panel, will cause the pll3_pfd1_540m PFD to be switched away from its
nominal rate to 288 MHz.
This has no negative side effects, as there are no other children to
this PFD. Still, to avoid surprises, it might be preferrable to switch
to the designated video PLL (pll5_video_div) as clock source for the
LCDIF pixel clock.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>