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  1. Oct 08, 2016
  2. Oct 06, 2016
    • Boris Ostrovsky's avatar
      xen/x86: Update topology map for PV VCPUs · a6a198bc
      Boris Ostrovsky authored
      
      
      Early during boot topology_update_package_map() computes
      logical_pkg_ids for all present processors.
      
      Later, when processors are brought up, identify_cpu() updates
      these values based on phys_pkg_id which is a function of
      initial_apicid. On PV guests the latter may point to a
      non-existing node, causing logical_pkg_ids to be set to -1.
      
      Intel's RAPL uses logical_pkg_id (as topology_logical_package_id())
      to index its arrays and therefore in this case will point to index
      65535 (since logical_pkg_id is a u16). This could lead to either a
      crash or may actually access random memory location.
      
      As a workaround, we recompute topology during CPU bringup to reset
      logical_pkg_id to a valid value.
      
      (The reason for initial_apicid being bogus is because it is
      initial_apicid of the processor from which the guest is launched.
      This value is CPUID(1).EBX[31:24])
      
      Signed-off-by: default avatarBoris Ostrovsky <boris.ostrovsky@oracle.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarDavid Vrabel <david.vrabel@citrix.com>
      a6a198bc
    • Russell King's avatar
      ARM: fix delays · fb833b1f
      Russell King authored
      
      
      Commit 215e362d ("ARM: 8306/1: loop_udelay: remove bogomips value
      limitation") tried to increase the bogomips limitation, but in doing
      so messed up udelay such that it always gives about a 5% error in the
      delay, even if we use a timer.
      
      The calculation is:
      
      	loops = UDELAY_MULT * us_delay * ticks_per_jiffy >> UDELAY_SHIFT
      
      Originally, UDELAY_MULT was ((UL(2199023) * HZ) >> 11) and UDELAY_SHIFT
      30.  Assuming HZ=100, us_delay of 1000 and ticks_per_jiffy of 1660000
      (eg, 166MHz timer, 1ms delay) this would calculate:
      
      	((UL(2199023) * HZ) >> 11) * 1000 * 1660000 >> 30
      		=> 165999
      
      With the new values of 2047 * HZ + 483648 * HZ / 1000000 and 31, we get:
      
      	(2047 * HZ + 483648 * HZ / 1000000) * 1000 * 1660000 >> 31
      		=> 158269
      
      which is incorrect.  This is due to a typo - correcting it gives:
      
      	(2147 * HZ + 483648 * HZ / 1000000) * 1000 * 1660000 >> 31
      		=> 165999
      
      i.o.w, the original value.
      
      Fixes: 215e362d ("ARM: 8306/1: loop_udelay: remove bogomips value limitation")
      Cc: <stable@vger.kernel.org>
      Reviewed-by: default avatarNicolas Pitre <nico@linaro.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      fb833b1f
    • netmonk@netmonk.org's avatar
      sparc: fixing ident and beautifying code · 98e98eb6
      netmonk@netmonk.org authored
      
      
      Good evening,
      
      Following LinuxCodingStyle documentation and with the help of Sam, fixed
      severals identation issues in the code, and few others cosmetic changes
      
      And last and i hope least fixing my name :)
      
      Signed-off-by : Dominique Carrel <netmonk@netmonk.org>
      Acked-by: default avatarSam Ravnborg <sam@ravnborg.org>
      
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      98e98eb6
    • chris hyser's avatar
      sparc64: Enable setting "relaxed ordering" in IOMMU mappings · aa7bde1a
      chris hyser authored
      
      
      Enable relaxed ordering for memory writes in IOMMU TSB entry from
      dma_4v_alloc_coherent(), dma_4v_map_page() and dma_4v_map_sg() when
      dma_attrs DMA_ATTR_WEAK_ORDERING is set. This requires PCI IOMMU I/O
      Translation Services version 2.0 API.
      
      Many PCIe devices allow enabling relaxed-ordering (memory writes bypassing
      other memory writes) for various DMA buffers. A notable exception is the
      Mellanox mlx4 IB adapter. Due to the nature of x86 HW this appears to have
      little performance impact there. On SPARC HW however, this results in major
      performance degradation getting only about 3Gbps. Enabling RO in the IOMMU
      entries corresponding to mlx4 data buffers increases the throughput to
      about 13 Gbps.
      
      Orabug: 19245907
      
      Signed-off-by: default avatarChris Hyser <chris.hyser@oracle.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      aa7bde1a
    • chris hyser's avatar
      sparc64: Enable PCI IOMMU version 2 API · 8914391b
      chris hyser authored
      
      
      Enable Version 2 of the PCI IOMMU API needed for advanced features
      such as PCI Relaxed Ordering and greater than 2 GB DMA address
      space per root complex.
      
      Signed-off-by: default avatarChris Hyser <chris.hyser@oracle.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8914391b
    • Paul Gortmaker's avatar
      sparc: migrate exception table users off module.h and onto extable.h · cdd4f4c7
      Paul Gortmaker authored
      
      
      These files were only including module.h for exception table
      related functions.  We've now separated that content out into its
      own file "extable.h" so now move over to that and avoid all the
      extra header content in module.h that we don't really need to compile
      these files.
      
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: sparclinux@vger.kernel.org
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cdd4f4c7
  3. Oct 05, 2016
  4. Oct 04, 2016
  5. Oct 02, 2016
  6. Oct 01, 2016
    • Paul Burton's avatar
      MIPS: CM: Fix mips_cm_max_vp_width for non-MT kernels on MT systems · 6605d156
      Paul Burton authored
      
      
      When discovering the number of VPEs per core, smp_num_siblings will be
      incorrect for kernels built without support for the MIPS MultiThreading
      (MT) ASE running on systems which implement said ASE. This leads to
      accesses to VPEs in secondary cores being performed incorrectly since
      mips_cm_vp_id calculates the wrong ID to write to the local "other"
      registers. Fix this by examining the number of VPEs in the core as
      reported by the CM.
      
      This patch presumes that the number of VPEs will be the same in each
      core of the system. As this path only applies to systems with CM version
      2.5 or lower, and this property is true of all such known systems, this
      is likely to be fine but is described in a comment for good measure.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14338/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6605d156
  7. Sep 30, 2016
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