- Nov 22, 2011
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Daniel Mack authored
Replace the manual register restore mechanism in cs4270.c and call the generic snd_soc_cache_sync() handler instead. This factors code out in favour of core facilities and also fixes a bus confusion that is most probably caused by intermixing i2c-regmap functions and i2c_smbus_* accessors. Signed-off-by:
Daniel Mack <zonque@gmail.com> Reported-and-tested-by:
Sven Neumann <s.neumann@raumfeld.com> Acked-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Mark Brown <broonie@opensource.wolfsonmicro.com>
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Axel Lin authored
In the case of ((max9877_regs[reg] >> shift) & mask) != val but ((max9877_regs[reg2] >> shift) & mask) == val2, current code does not update the registers. Fix the logic to update registers if either val or val2 is changed. Signed-off-by:
Axel Lin <axel.lin@gmail.com> Signed-off-by:
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Axel Lin authored
According to the datasheet: The BIT[5:4] of ADC Control Register 2 is to control the word width. 00 = 25 Bits 01 = 20 Bits 10 = 16 Bits 11 = Invalid Thus, the AD1836_ADC_WORD_OFFSET should be defined as 4. Signed-off-by:Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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- Nov 21, 2011
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Mark Brown authored
Signed-off-by:
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- Nov 20, 2011
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Axel Lin authored
Signed-off-by:
Alexander Sverdlin <subaparts@yandex.ru> Signed-off-by:
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Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent reading more data than actually is in the array. Signed-off-by:Clemens Ladisch <clemens@ladisch.de>
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Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent reading more data than actually is in the arrays. Signed-off-by: -
Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent reading more data than actually is in the array. Signed-off-by: -
Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent reading more data than actually is in the arrays. Signed-off-by: -
Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent reading more data than actually is in the array. Signed-off-by: -
Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent the last entry from being omitted. Signed-off-by: -
Clemens Ladisch authored
Give the correct number of entries to TLV_DB_RANGE_HEAD to prevent reading more data than actually is in the array. Signed-off-by:
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- Nov 17, 2011
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Timo Juhani Lindfors authored
This patch makes it possible to set DAI mode to its currently applied value even if codec is active. This is necessary to allow aplay -t raw -r 44100 -f S16_LE -c 2 < /dev/urandom & alsactl store -f backup.state alsactl restore -f backup.state to work without returning errors. This patch is based on a patch sent by Klaus Kurzmann <mok@fluxnetz.de>. Signed-off-by:
Timo Juhani Lindfors <timo.lindfors@iki.fi> Signed-off-by:
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- Nov 14, 2011
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Johannes Stezenbach authored
The coefficient RAM must be saved in a shadow so it can be restored when the codec is powered on using regulator_bulk_enable(). Signed-off-by:
Johannes Stezenbach <js@sig21.net> Signed-off-by:
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- Nov 08, 2011
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Axel Lin authored
WM9081_BIAS_ENA is the bit[1] of WM9081_BIAS_CONTROL_1 register (05h). Current code incorrectly write it to WM9081_VMID_CONTROL(04h) register. Signed-off-by:
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Axel Lin authored
VMID Divider Enable and Select is controlled by BIT[2:1] of WM9081_VMID_CONTROL register (04h). Current code reads wrong register (WM9081_BIAS_CONTROL_1) for setting VMID 2*240k. Signed-off-by:
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- Nov 04, 2011
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Mark Brown authored
Occasionally we may see an accessory reported before we have a stable impedance for the accessory. If this happens then reread the status in order to ensure that the handler can take the appropriate action for the status change. Signed-off-by: -
Mark Brown authored
The field is no longer initialised so this will crash if running on wm8958. Reported-by:
Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by:
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Mark Brown authored
The field is no longer initialised so this will crash if running on wm8958. Reported-by:
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- Nov 01, 2011
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Mark Brown authored
Signed-off-by: -
Mark Brown authored
Since there is no current software control for these they would otherwise be left enabled, consuming power. Signed-off-by: -
Mark Brown authored
The WM8962 has a separate software reset for the PLL registers. Ensure that these are reset also on startup. Signed-off-by:
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- Oct 31, 2011
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Paul Gortmaker authored
Lots of sound drivers were getting module.h via the implicit presence of it in <linux/device.h> but we are going to clean that up. So fix up those users now. Signed-off-by:Paul Gortmaker <paul.gortmaker@windriver.com>
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Mark Brown authored
We can't just pass back the return value of snd_soc_update_bits() as it will be 1 if a bit changed rather than zero. Signed-off-by: -
Hong Xu authored
Set `invert' bit for Capture Switch. Otherwise analogue is muted when Capture Switch is ON. Signed-off-by:
Hong Xu <hong.xu@atmel.com> Signed-off-by:
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Axel Lin authored
Current implementation in wm8711_set_dai_fmt always clear BIT[3:2] (the Input Audio Data Bit Length Select) of WM8711_IFACE(07h) register. Input Audio Data Bit Length Select bits are set by wm8711_hw_params, we should leave BIT[3:2] untouched in wm8711_set_dai_fmt. Signed-off-by:
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Axel Lin authored
The Input Audio Data Bit Length Select is controlled by BIT[3:2] of WM8711_IFACE(07h) register. Current code incorrectly masks BIT[1:0] which is for Audio Data Format Select. Signed-off-by:
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- Oct 27, 2011
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Axel Lin authored
According to the datasheet: Page0 / Register8: Audio Serial Data interface Control Register A BIT 7: Bit Clock Directional Control 0: Bit clock is an input (slave mode) 1: Bit clock is an output (master mode) BIT 6: Word Clock Directional Control 0: Word clock is an input (slave mode) 1: Word clock is an output (master mode) Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode, but does not clear these bits for slave mode. Signed-off-by: -
Axel Lin authored
According to the datasheet: Digital Audio Interface Format (07h) register: BIT6: Master/slave mode 0: Slave 1: Master Current code sets TLV320AIC23_MS_MASTER bit for master mode, but does not clear it for slave mode. Signed-off-by:
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Axel Lin authored
According to the datasheet: BCLK is controlled by BIT[4:2] of WM8940_CLOCK(06h) register. Signed-off-by:
Chris Paulson-Ellis <chris@edesix.com> Signed-off-by:
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Axel Lin authored
Reported-by:
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- Oct 22, 2011
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Axel Lin authored
codec->hw_write is broken now, convert codec->hw_write to snd_soc_write. The hardware has 2 banks of registers sharing a section in I2C register space. The 1st bank is the primary one and is cached. The 2nd bank is for loading coefficients only and they do not need cache. These coefficients registers are therefore direct writes. Thus we set cache_bypass flag to deal with this before calling snd_soc_write. Signed-off-by:
Liam Girdwood <lrg@ti.com> Signed-off-by:
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Axel Lin authored
Ensure all mask bits are clear before setting new value. Signed-off-by:
Dong Aisheng <b29396@freescale.com> Acked-by:
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Axel Lin authored
Signed-off-by:
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Ashish Chavan authored
DA7210 has three line outputs. OUT1 Left, OUT1 Right and OUT2 (mono). This patch adds support for gain controls for these three line outs. It also adds support for overall DAC gain control. Signed-off-by:
Ashish Chavan <ashish.chavan@kpitcummins.com> Signed-off-by:
David Dajun Chen <dchen@diasemi.com> Acked-by:
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Ashish Chavan authored
This patch adds support for DAPM covering all inputs and outputs as well as ADC and DAC. Signed-off-by:
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- Oct 21, 2011
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Axel Lin authored
We have defined SGTL5000_LINREG_VDDD_MASK in sgtl5000.h, use it instead of hardcoded (0x1 << 4) - 1 for the mask. Signed-off-by:
Wolfram Sang <w.sang@pengutronix.de> Acked-by:
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Axel Lin authored
Otherwise calling ldo_regulator_remove() does not unregister regulator and free memories. Signed-off-by:
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- Oct 20, 2011
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Axel Lin authored
Signed-off-by:
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Axel Lin authored
Signed-off-by:
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