The edp-phy control is a part of the General Register Files and
with a recent patch in 4.6 the phy driver can now also handle this
correctly, so move the dts node under the GRF as well.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Similar to the pmu, the general register files contain a lot of different
setting bits grouped into general registers, but also some somewhat special
entities like the controls for some phy-blocks or the io-voltage control.
To be able to move these blocks under the grf node where they actually
belong, make it a simple-mfd.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch add the i2c dt nodes for rk3228 SoCs.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The amount of available memory is clearly a board-specific value, so
the core per-soc dtsi should not define a default of any sort.
Therefore move the memory-nodes to the two board files.

Also fix the amount of memory on Kylin (512MB instead of 1GB).
While in most cases the bootloader will override this with the
actual amount of memory, there is no need to keep known wrong values
in the board-dts.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

After hooking up panel and backlight informations, enable the
edp on veyron chromebooks now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

Jerry and Speedy don't need any special handling wrt the backlight or
panel, so only need their backlight and panel-regulators hooked up.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

Pinky boards don't have the hotplug pin connected. So remove the
hotplug pinctrl setting and enable the force-hpd option, to allow
them to find the display too.

While on speedy boards, the hotplug pin is connected, judging by comments
in a chromeos change it seems the "panels HPD voltage is too low to be
detected", so it also needs the forced hotplug, as we of course also know
that a display is connected.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

The pwm for Minnie's backlight needs to be above 1%, so adapt the start
of non-zero brightness accordingly. Minnie is also using a different
panel, so re-set the compatible property.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

The panel which jaq uses requires the pwm duty cycle larger than 3%,
when the backlight status from power off to power on, otherwise the
backlight will flush, so we modify the second brightness-level to 8,
and when the backlight from power off to power on the pwm duty cycle
will larger than 3%.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

Many Veyron chromebooks share the same panel type, so define the core
settings for all of them and allow the few runaways to override it later.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

The panels need a bit of time to actually turn on. If this isn't
observed, this results in problems when trying talk to the panels
and thus produces detection errors. 100ms seem to be a safe value
for the time being.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

The edp hotplug pin is fixed on the soc side, anybody wanting to use it
will need the same definition anyway, so move it to a common location.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

Add the rk3288 edp node and its hooks into the display-subsystem.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

Add the core device node of the edp-phy on rk3288 socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>

The cpu_leakage efuse on rk3288 did get it right including the
unitname but on both rk3066a and rk3188 it was missing, fix that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>

The mipi controller node does contain an unused reg property as well as
unnecessary #address-cells and #size-cells properties for subnodes
not using addresses, so remove those to also make dtc happy.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>

Drop superfluous #address-cells and #size-cells, rename
key-nodes to individual names and also use the key constants
intead of numbers.

Reported-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>

The usbphy subnodes do have a reg property but no unitname, add them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>

The power-domain sub-nodes do have reg properties, but so far are
missing the expected unit names. So add the missing ones.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>

The generic operating points specified in rk3288.dtsi are specified by
Rockchip as conservative and for all cases.

In contrast the Veyron ChromeOS devices are supposed to use a special
chip variant often called rk3288-c and use different operating points
in their kernel also including a higher max frequency.

So override the operating points for veyron devices.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

Only one of "broken-cd" and "non-removable" should be supplied
according to Documentation/devicetree/bindings/mmc/mmc.txt.
Obviously emmc and sdio-wifi are non-removable devices, while
broken-cd is for removable device whose card detect pin is broken.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch enables the tsadc for rk3228 evb board.

The rk3228 evb board uses the CRU to reset the chip since it hasn't the
PMIC to connect it, and TSHUT is low active on evb board.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch adds the thermal needed main information for rk3228 SoCS.

Basically has the following content:

1) TSADC controller:
Add the needed attributes for rk3036 TSADC controller.

Especially for the TSHUT, in some cases if we are unable to shut it down
in orderly fashion (says: kernel is stuck holding a lock or similar), then
hardware TSHUT will reset it.
If the temperature is over 95C over a period of time the thermal shutdown
of the tsadc is invoked with can either reset the entire chip via the CRU,
or notify the PMIC via a GPIO. This should be set in the specific board.

2) Thermal zones:
Add the needed device mode for thermal generic framework.
Detail in Documentation/devicetree/bindings/thermal/thermal.txt.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The MIPI controllers are part of the VIO power domain so add the
necessary property to indicate this for the controller we support.

Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

These must be translated from the values in the TRM by subtracting 32,
which has not been done.  The SPDIF interrupt is also off-by-one.

Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This isn't currently used by the driver but the correct value is 19
since DSIHOST0 is 51 in the TRM and the GIC offset requires 32 to be
subtracted.

Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Enable the recently added vop and hdmi nodes on the rk3036-kylin board.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the Innosilicon hdmi node for HDMI display.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The rk3036 support two overlay plane and one hwc plane,
it supports IOMMU, and its IOMMU same as rk3288's.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

If enabling the hsmci regulator on card detection, the board can reboot
on sd card insertion. Keeping the regulator always enabled fixes this
issue.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Fixes: 8d545f32 ("ARM: at91/dt: sama5d4 xplained: add regulators for v(q)mmc1 supplies")
Cc: stable@vger.kernel.org #4.3 and later
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

If enabling the hsmci regulator on card detection, the board can reboot
on sd card insertion. Keeping the regulator always enabled fixes this
issue.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Fixes: 1b53e341 ("ARM: at91/dt: sama5d3 xplained: add fixed regulator for vmmc0")
Cc: stable@vger.kernel.org #4.3 and later
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

This will be needed for UniPhier PH1-LD11 and PH1-LD20 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Just for consistent coding style.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Initial commit for PH1-Pro4 Sanji board support.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Initial commit for PH1-Pro4 Ace board support.

Note:
There are two variants for the amount of DDR memory; 1GB or 2GB.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This is used for on-board inter-connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This board has an EEPROM (STMicroelectronics M24C64-WMN6TP) connected
to the I2C channel 0 of the SoC.  Its slave address is 0x54.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This property is used in common by several boards.  Move it to the
common place (uniphier-support-card.dtsi).  If necessary, each board
can still override the property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>