- Nov 24, 2009
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Thomas Gleixner authored
The typename member of struct irq_chip was kept for migration purposes and is obsolete since more than 2 years. Fix up the leftovers. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linuxppc-dev@ozlabs.org Acked-by:
Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Thomas Gleixner authored
SPIN_LOCK_UNLOCKED is deprecated. Init the lock array at runtime instead. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
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Thomas Gleixner authored
The ioctl is only used for powermac systems and reads a partition number from an array which is initialized at boot time way before the nvram code is initialized. So it's safe to switch to unlocked_ioctl. Signed-off-by:
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roel kluin authored
size_t len cannot be less than 0. Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Acked-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
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- Nov 20, 2009
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Kumar Gala authored
Add basic support for the P4080 DS reference board. None of the data path devices (ethernet, crypto, pme) are support at this time. Signed-off-by:Kumar Gala <galak@kernel.crashing.org>
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Martyn Welch authored
Add support for NVRAM on GE Fanuc's PPC9A. Signed-off-by:
Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by:
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Martyn Welch authored
Add support for NVRAM on GE Fanuc's SBC310. Signed-off-by:
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Martyn Welch authored
This patch enables the NVRAM found on the GE Fanuc SBC610 Signed-off-by:
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Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Re-write the code so its more standalone and fixed some issues: * Bump'd # of CAM entries to 64 to support e500mc * Make the code handle MAS7 properly * Use pr_cont instead of creating a string as we go Signed-off-by: -
Kumar Gala authored
Introduce new FSL_SOC_BOOKE Kconfig to handle both 85xx and QorIQ based chips. Signed-off-by:
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- Nov 12, 2009
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Anton Vorontsov authored
Export is needed for modular builds, and a static inline stub is needed for non-MPC83xx builds. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
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Anton Vorontsov authored
Simply add power management controller nodes and sleep properties. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Anton Vorontsov authored
This patch adds needed nodes and properties to support suspend/resume on the MPC8610HPCD boards. There is a dedicated switch (SW9) that is used to wake up the boards. By default the SW9 button is routed to IRQ8, but could be re-routed (via PIXIS) to sreset. With 'no_console_suspend' kernel command line argument specified, the board is also able to wakeup upon serial port input. Signed-off-by:
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Anton Vorontsov authored
- Add power management controller nodes; - Add interrupts for RTC nodes, the RTC interrupt may be used as a wakeup source; - Add sleep properties (DEVDISR bit mask) and sleep-nexus nodes. Signed-off-by:
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Anton Vorontsov authored
This patch adds suspend/resume support for MPC8540 and MPC8641D- compatible CPUs. To reach sleep state, we just write the SLP bit into the PM control and status register. So far we don't support Deep Sleep mode as found in newer MPC85xx CPUs (i.e. MPC8536). It can be relatively easy implemented though, and for it we reserve 'mem' suspend type. Signed-off-by:
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Anton Vorontsov authored
So far the driver is used to reset QE upon resume, which is needed on 85xx. Later we can move some QE initialization steps into probe(). Signed-off-by:
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Anton Vorontsov authored
This is needed to avoid ugly #ifdefs in drivers. Also update fsl_qe_udc driver so that now it doesn't define its own versions that cause build breakage when the generic stubs are used. Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by:
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Anton Vorontsov authored
The bits are generic to CPM devices, so let's move them to the common header file, so drivers won't need to privately reintroduce another bunch of the same bits (as we can't include cpm2.h header together with cpm1.h). Signed-off-by:
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Anton Vorontsov authored
struct mcc defined in both immap_qe.h and immap_cpm2.h, so they will conflic when included in a single file. The mcc struct is easy to deal with, since it isn't used in any driver (yet), so let's just rename QE version to qe_mcc. The ucb_ctlr is a bit trickier, since it is used by fsl_qe_udc driver, and the driver supports both CPM and QE UDCs, plus the QE version is used to form a bigger immap struct. I don't want to touch too much of USB code in this series, so for now let's just copy most generic version into the common cpm.h header, later we'll create cpm_usb.h where we'll place common USB structs that are used by QE/CPM UDC and QE Host drivers (FHCI). And as for the structs in qe.h and cpm2.h, just prefix them with qe_ and cpm_. Signed-off-by:
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Anton Vorontsov authored
When cpm2.h included into spi_mpc8xxx driver, the SPI defines in the header conflict with defines in the driver. We don't need them in the header file, so remove them. Plus remove "struct spi", we'll use a better version in the driver. Signed-off-by:
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Poonam Aggrwal authored
P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
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Anton Vorontsov authored
It appears that QE shuts down on all MPC85xx CPUs (i.e. MPC8568 and MPC8569) and thus needs reset upon resume. So modify qe_alive_during_sleep() to account that. Signed-off-by:
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Anton Vorontsov authored
For MPC8569 CPUs we'll need to reset QE after each suspend, so make qe_reset() code path suitable for repeated invocation, that is: - Don't initialize rheap structures if already initialized; - Don't allocate muram for SDMA if already allocated, just reinitialize registers with previously allocated muram offset; - Remove __init attributes from qe_reset() and cpm_muram_init(); Signed-off-by:
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Poonam Aggrwal authored
This patch creates the dts files for each core and splits the devices between the two cores for P2020RDB. core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0, core1 has L2, dma2, eth0, pci1, msi. MPIC is shared between two cores but each core will protect its interrupts from other core by using "protected-sources" of mpic. Signed-off-by:
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Anton Vorontsov authored
This is needed to avoid #ifdefs in MPC85xx suspend/resume code. Signed-off-by:
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Anton Vorontsov authored
MPC8569 CPUs have four QE RISCs, so we need to increase MAX_QE_RISC constant, otherwise qe_upload_firmware() fails at sanity checking. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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- Nov 11, 2009
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Olof Johansson authored
pasemi_defconfig hasn't been updated for a year. Mostly a refresh of defaults, but this also disables 64K pages. Signed-off-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
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- Nov 05, 2009
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Kumar Gala authored
Updated mpc85xx_{smp_}defconfig to enable: * XES_MPC85xx board * PCI MSI * RapidIO Signed-off-by: -
Kim Phillips authored
Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Anton Vorontsov authored
u-boot partition size should be 0x80000 (512 KB), not 0x8000 (32 KB). Signed-off-by:
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Anton Vorontsov authored
This patch fixes USB GPIOs numbers for MPC8569E-MDS boards, plus according to the latest HW Getting Started Guide (rev 3.3, pilot boards), USB "POWER" GPIO polarity has changed, it is no longer inverted. This patch makes USB Host somewhat work on pilot boards, though there are still some problems with determining devices speed and long bulk transfers. Reported-by:
Liu Yu <Yu.Liu@freescale.com> Signed-off-by:
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Roel Kluin authored
Prevent NULL dereference if kmalloc() fails. Also clean up if of_mdiobus_register() returns an error. Signed-off-by:
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Paul Gortmaker authored
The PCI-e addressing was originally patterned of the MPC8548CDS which has PCI1, PCI2, and PCI-e. Since this board only has PCI1 and PCI-e, it makes more sense to be similar to the MPC8568MDS board. This does that by cutting the PCI/PCI-e I/O sizes from 16MB to 8MB and pulling the PCI-e I/O range back to 0xe280_0000 (the hole where PCI2 I/O would have been). This also fixes a typo where an extra zero made an 8MB range a 128MB range, removes the hole left by PCI2 from the aliases, and sets the clocks to match the oscillators that are actually on the board. With accompanying u-boot updates, PCI-e has been validated with both a sky2 card (1148:9e00) and an e1000 card (8086:108b). Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Andre Detsch authored
Patch f598282f exposed a problem in powerpc MSI-X functionality, making network interfaces such as ixgbe and cxgb3 stop to work when MSI-X is enabled. RX interrupts were not being generated. The problem was caused because MSI irq was not being effectively unmasked after device initialization. Signed-off-by:
Andre Detsch <adetsch@br.ibm.com> Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Benjamin Herrenschmidt authored
Doing so causes xtime to be negative which crashes the timekeeping code in funny ways when doing suspend/resume Signed-off-by: -
Alexander Graf authored
Following S390's good example we should use hrtimers for the decrementer too! This patch converts the timer from the old mechanism to hrtimers. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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