- Nov 05, 2018
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Sergei Shtylyov authored
The "official" Condor boards have always been wired to mount NFS via GEther, not EtherAVB -- the boards resoldered for EtherAVB were local to Cogent Embedded, so we've been having an unpleasant situation where a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY extension board is plugged in). Switch from EtherAVB to GEther at last! Fixes: 8091788f ("arm64: dts: renesas: condor: add EtherAVB support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Kuninori Morimoto authored
hscif2 has 4 dmas, but has only 2 dma-names. This patch add missing dma-names. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Fixes: e0f0bda7 ("arm64: dts: renesas: r8a7795: sort subnodes of the soc node") Signed-off-by:
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- Sep 26, 2018
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Takeshi Kihara authored
Based on a similar patch of the R8A7796 device tree by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by:
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Ulrich Hecht authored
Adds LVDS decoder, HDMI encoder and connector for the Draak board. The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and EXTAL externals clocks. Two of them are provided to the SoC on the Draak board, hook them up in DT. Signed-off-by:
Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
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Laurent Pinchart authored
Add the LVDS decoder, HDMI encoder, VGA encoder and HDMI and VGA connectors, and wire up the display-related nodes with clocks, pinmux and regulators. The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and EXTAL externals clocks. Two of them are provided to the SoC on the Ebisu board, hook them up in DT. Signed-off-by:
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Kieran Bingham authored
The r8a77995 D3 platform has 2 LVDS channels connected to the DU. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by:
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Laurent Pinchart authored
The R8A77990 (E3) platform has one RGB output and two LVDS outputs connected to the DU. Add the DT nodes for the DU, LVDS encoders and supporting VSP and FCP. Signed-off-by:
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- Sep 25, 2018
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Sergei Shtylyov authored
Describe TPU in the R8A779{7|8}0 device trees. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by:Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
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Yoshihiro Shimoda authored
R-Car Gen3 SoCs need to enable/deassert clocks/resets of both usb 2.0 host (included phy) and peripheral. Otherwise, other side device cannot work correctly. So, this patch revises properties of clocks and resets. After that, each device driver can enable/deassert clocks/resets by its self. Notes: - To work the renesas_usbhs driver correctly when host side drivers are disabled and the renesas_usbhs driver doesn't have multiple clock management, this patch doesn't change the order of the clocks property in each hsusb node. - This patch doesn't have any side-effects even if the renesas_usbhs driver doesn't have reset_control and multiple clock management. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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- Sep 24, 2018
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Kuninori Morimoto authored
It can't boot without bootargs settings on Uboot on ulcb board. This patch adds missing default bootargs. ulcb BSP can overwrite it by own UBoot settings. Signed-off-by:
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- Sep 19, 2018
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Sergei Shtylyov authored
Describe CMTs in the R8A779{7|8}0 device trees. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by: -
Wolfram Sang authored
The PMIC and EEPROM can operate at 400kHz, so use this speed. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
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Magnus Damm authored
For R-Car V3H hook up SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS1 to match information in the R-Car Gen3 Rev.1.00 (April 2018) datasheet. Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Magnus Damm authored
For R-Car E3 hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car H3. This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet. Signed-off-by:
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- Sep 17, 2018
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Jacopo Mondi authored
Add HDMI and CVBS inputs device nodes to R-Car E3 Ebisu board. Both HDMI and CVBS inputs are connected to an ADV7482 video decoder hooked to the SoC CSI-2 receiver port. Signed-off-by:
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- Sep 14, 2018
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Geert Uytterhoeven authored
The thermal device is supposed to be always enabled. As the default value of the status property is "okay", there is no need to make this explicit in SoC-specific .dtsi files where no override is involved. Signed-off-by:
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- Sep 13, 2018
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Hoan Nguyen An authored
The r8a77965 has a single FDP1 instance. Signed-off-by:
Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by:
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Geert Uytterhoeven authored
- Device nodes with unit addresses are sorted by unit address, - Device nodes without unit addresses and references are sorted alphabetically. Signed-off-by: -
Wolfram Sang authored
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0. Even previously stubborn cards work fine. Transfer rates were >60MB/s. Signed-off-by:
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Takeshi Kihara authored
This patch adds SYS-DMAC{0,1,2} device nodes for the R8A77990 SoC. Signed-off-by: -
Takeshi Kihara authored
Add device nodes for I2C ch[0-7] to R-Car E3 R8A77990 device tree. Signed-off-by:
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Koji Matsuoka authored
Add device nodes for VIN4, VIN5 and CSI40 to R-Car E3 R8A77990 device tree. Signed-off-by:
Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by:
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Geert Uytterhoeven authored
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power domains, and resets properties. Signed-off-by:
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Geert Uytterhoeven authored
To preserve by-address-per-group sort order. Fixes: 0f6d237c ("arm64: dts: renesas: r8a7795: add ccree to device tree") Signed-off-by:
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Takeshi Kihara authored
Add the device node for the external SCIF_CLK, and describe the clock inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2, which can increase serial clock accuracy. The presence of the SCIF_CLK crystal and its clock frequency depend on the actual board. Signed-off-by:
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Geert Uytterhoeven authored
Use the SoC-specific CPG/MSSR include file to allow future use of R8A77990_CLK_* symbols. Replace the hardcoded power domain indices by R8A77990_PD_* symbols. Signed-off-by:
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Geert Uytterhoeven authored
The comments describing the non-default switch settings to use SATA are confusing: 'Off' refers to the switch position, not to the MD12 logic value, while the parentheses suggest otherwise. Rephrase to fix this. Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA") Signed-off-by: -
Geert Uytterhoeven authored
usb2_phy1 accidentally uses the same clock/reset as usb2_phy0. Fixes: b5857630 ("arm64: dts: renesas: r8a77965: add usb2_phy nodes") Signed-off-by:
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Geert Uytterhoeven authored
Should be "renesas,usbhs-r8a77965", not "renesas,usbhs-r8a7796". Fixes: a06e8af8 ("arm64: dts: renesas: r8a77965: add HS-USB node") Signed-off-by:
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Geert Uytterhoeven authored
To preserve alphabetical sort order. Fixes: 4c529600 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support") Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
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Geert Uytterhoeven authored
To preserve alphabetical sort order. Fixes: 4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support") Signed-off-by: -
Geert Uytterhoeven authored
Signed-off-by:
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Eugeniu Rosca authored
This is based on the existing KF device tree sources: $ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts Signed-off-by:
Eugeniu Rosca <erosca@de.adit-jv.com> Signed-off-by:
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Sergei Shtylyov authored
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor board. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
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Sergei Shtylyov authored
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device tree. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by:
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Biju Das authored
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
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Biju Das authored
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi. Signed-off-by:
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Biju Das authored
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi. Signed-off-by:
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Fabrizio Castro authored
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly to what was done for the r8a7796 with commit 41dbbf0c ("arm64: dts: r8a7796: Add FCPF and FCPV instances"), commit 69490bc9 ("arm64: dts: renesas: r8a7796: Point FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0 ("arm64: dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0"). Signed-off-by:
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Biju Das authored
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1). This work is based on similar work done on the R8A7796 SoC by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>. Signed-off-by:
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