- Nov 30, 2021
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Abhinav Kumar authored
Add and also update the email addresses to prepare for the transition to the new ones. Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Acked-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1637363725-17732-1-git-send-email-quic_abhinavk@quicinc.com Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Abhinav Kumar authored
Adding myself as a designated reviewer to assist with the code reviews for the changes coming into MSM DRM. Acked-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Krishna Manikandan authored
In the current implementation, substring comparison using device node name is used to find mdp node during driver probe. Use compatible string list instead of node name to get mdp node from the parent mdss node. Signed-off-by:
Krishna Manikandan <quic_mkrishn@quicinc.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Changes in v2: - Use compatible lists instead of duplicate string check (Stephen Boyd) Changes in v3: - Use match tables to find the mdp node (Stephen Boyd) Changes in v4: - Drop EXPORT_SYMBOL (Dmitry Baryshkov) Link: https://lore.kernel.org/r/1636541507-5144-1-git-send-email-quic_mkrishn@quicinc.com Signed-off-by:
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Bjorn Andersson authored
In addition to the other 7xxx INTF interrupt regions, SM8350 has additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define these. The 7xxx naming scheme of the bits are kept for consistency. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Robert Foss <robert.foss@linaro.org> Reviewed-by:
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Bjorn Andersson authored
Since '8ede2ecc ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets")' the hpd_high member of struct dp_usbpd has been write-only. Let's clean up the code a little bit by removing the writes as well. Signed-off-by:
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Rob Clark authored
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Rob Clark authored
If you don't realize is_a650_family() also encompasses a660 family, you'd think that the debug buffer is double allocated. Add a comment to make this more clear. Signed-off-by:
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Rob Clark authored
It appears to be a GMU fw build option whether it does anything with debug and log buffers, but if they are all zeros it won't add anything to the devcore size. Signed-off-by:
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Rob Clark authored
This also includes a history of start index of the last 8 messages on each queue, since parsing backwards to decode recently sent HFI messages is hard(ish). Signed-off-by:
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Rob Clark authored
Turn it into a thing we can use to snapshot other GMU buffers. Signed-off-by:
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Rob Clark authored
We don't expect either of these conditions to ever be true, so let's get shouty if they are. Signed-off-by:
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- Nov 28, 2021
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Akhil P Oommen authored
Capture gmu log in coredump to enhance debugging. Signed-off-by:
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Rob Clark authored
Re-work the boost and idle clamping to use PM QoS requests instead, so they get aggreggated with other requests (such as cooling device). This does have the minor side-effect that devfreq sysfs min_freq/ max_freq files now reflect the boost and idle clamping, as they show (despite what they are documented to show) the aggregated min/max freq. Fixing that in devfreq does not look straightforward after considering that OPPs can be dynamically added/removed. However writes to the sysfs files still behave as expected. v2: Use 64b math to avoid potential 32b overflow Signed-off-by:
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Akhil P Oommen authored
Currently, we boost gpu freq after 25ms of inactivity. This regresses some of the 30 fps usecases where the workload on gpu (at 33ms internval) is very small which it can finish at the lowest OPP before the deadline. Lets increase this inactivity threshold to 50ms (same as the current devfreq interval) to fix this. Signed-off-by:
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Rob Clark authored
This was the one GPU related kernel buffer which was not given a debug name. Let's fix that. Signed-off-by:
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Rob Clark authored
Add a debugfs interface to ignore hw error irqs, in order to force fallback to sw hangcheck mechanism. Because the hw error detection is pretty good on newer gens, we need this for igt tests to test the sw hang detection. Signed-off-by:
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Rob Clark authored
Add some helpers for fence comparision, which handle rollover properly, and stop open coding fence seqno comparisions. Signed-off-by:
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Rob Clark authored
The remaining struct_mutex usage is just to serialize various gpu related things (submit/retire/recover/fault/etc), so replace struct_mutex with gpu->lock. Signed-off-by:
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Rob Clark authored
cur_ctx_seqno already does the same thing, but handles the edge cases where a refcnt'd context can live after lastclose. So let's not have two ways to do the same thing. Signed-off-by:
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Rob Clark authored
The struct_mutex locking is a remnant from the days before per-obj locks, and no longer needed. Signed-off-by:
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Dmitry Baryshkov authored
The "vdd" regulator was used by the mdp5 driver only on downstream kernels, where the GDSC is represented as a regulator. On all current kernels the MDSS_GDSC is implemented as the power domain, removing the need for this regulator. Remove it from the mdp5 driver. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Sankeerth Billakanti authored
The eDP sink on sc7280 supports ASSR and dp driver will enable ASSR in the source hardware. The driver needs to enable the ASSR field in the DPCD configuration register to avoid screen corruption. This change will enable ASSR if supported in the sink device. Signed-off-by:
Sankeerth Billakanti <quic_sbillaka@quicinc.com> Reviewed-by:
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Sankeerth Billakanti authored
The sc7280 eDP sink that supports downspread will fail link training if source does not enable SSC / downspread. This change will set the downspread bit in the DP sink if supported and indicate SSC support to the DP PHY driver. Signed-off-by:
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Sankeerth Billakanti authored
Add a macro to check for the max_downspread capability in drm_dp_helper. Signed-off-by:
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Sankeerth Billakanti authored
The eDP controller on SC7280 is similar to the eDP/DP controllers supported by the current driver implementation. SC7280 supports one EDP and one DP controller which can operate concurrently. This change adds the support for eDP and DP controller on sc7280. Signed-off-by:
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Sankeerth Billakanti authored
The Qualcomm SC7280 platform supports one eDP controller and a DP controller. This change will add the compatible string for both eDP and DP to msm dp-controller binding. Signed-off-by:
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Dmitry Baryshkov authored
There is no reason to set clock parents manually, use device tree to assign DSI/display clock parents to DSI PHY clocks. Dropping this manual setup allows us to drop repeating code and to move registration of hw clock providers to generic place. Signed-off-by:
Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20211006204828.1218225-2-dmitry.baryshkov@linaro.org Signed-off-by:
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Dmitry Baryshkov authored
Move DPHY/CPHY setting from msm_dsi_host_set_src_pll() to new function msm_dsi_host_set_phy_mode(). Signed-off-by:
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Dmitry Baryshkov authored
eDP driver is being removed, so drop bindings description. Signed-off-by:
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Dmitry Baryshkov authored
MSM DRM driver has support for eDP block present on MSM 8x74/8x84 SoC families. However since addition back in 2015 this driver received only generic fixes. No actual devices with these SoCs supported upstream (or by the community) seem to support eDP panels. Judging from downstream kernels the eDP was present only on MSM8974 LIQUID or on APQ8084 CDP. Remove this driver. Signed-off-by:
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Dmitry Baryshkov authored
Prepare for removing old eDP support present in 8x74/8x84 SoC families. No devices present in mainline support eDP ports. Signed-off-by:
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Dmitry Baryshkov authored
Do not cache hw_pipe's sblk in dpu_plane. Use pdpu->pipe_hw->cap->sblk directly. Signed-off-by:
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Dmitry Baryshkov authored
Do not cache hw_pipe's features in dpu_plane. Use pdpu->pipe_hw->cap->features directly. Signed-off-by:
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Dmitry Baryshkov authored
Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an interim configuration structure. Allocate it on stack instead. Signed-off-by:
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Dmitry Baryshkov authored
Simplify code surrounding CSC table setup by removing struct dpu_csc_cfg pointer from dpu_plane and getting it directly at the CSC setup time. Signed-off-by:
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Dmitry Baryshkov authored
struct dpu_hw_pipe_cfg represents an interim state during atomic update/color fill, so move it out of struct dpu_plane. Signed-off-by:
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Dmitry Baryshkov authored
The stage_cfg is not used outside of _dpu_crtc_blend_setup(), so remove the temporary config from global struct. Signed-off-by:
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Dmitry Baryshkov authored
Use plane->name instead of artificial pipe_name. Signed-off-by:
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Dmitry Baryshkov authored
The pipe_qos_cfg is used only in _dpu_plane_set_qos_ctrl(), so remove it from the dpu_plane struct and allocate it on stack when necessary. Signed-off-by:
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Dmitry Baryshkov authored
LUT levels are setup outside of setup_qos_ctrl, so remove them from the struct dpu_hw_pipe_qos_cfg. Signed-off-by:
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