This DTS file have initial support Samsung Aries based phones.
Initial version have support for:
 - sdcard
 - internal memory (present only on non 4g variant)
 - max8998 pmic and rtc
 - max17040 fuel gauge
 - gpio keys
 - fimd (no panel driver yet)
 - usb (peripherial mode)
 - wifi

Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Adds missing interrupt-controller property to gph2 block,
to silence following warnings during build:

    /soc/pinctrl@e0200000/gph2: Missing interrupt-controller or interrupt-map property

It's reguired by Samsung Aries boards, an S5PV210 based
Samsung Galaxy S (i9000) and Galaxy S 4G phones, which are added in next patches.

Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Remove no longer needed samsung thermal properties.

There should be no functional changes caused by this patch.

Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Secondary CPUs should have the same information in DeviceTree as booting
CPU from both correctness point of view and for possible hotplug
scenarios.

Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>

The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Fix other missing properties (clocks, OPP, clock latency) as well to
make it all work.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

The register address should be the full address of the rng, not the
offset from the start of the SCU.

Fixes: 5daa8212 ("ARM: dts: aspeed: Describe random number device")
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Olof Johansson <olof@lixom.net>

ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK
rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus
clock.

Based on Andy Duan's patch from the NXP kernel tree.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

The clocks for the 3 MMC controllers on pxa3xx platforms are CLK_MMC1,
CLK_MMC2 and CLK_MMC3. CLK_MMC is only for pxa2xx.

Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

The PXA3xx series features some extended GPIO banks which are named GPIO0_2,
GPIO1_2 etc. The PXA300, PXA310 and PXA320 have different numbers of such
pins, and they also have variant-specific register offsets.

Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

The PXA GPIO driver calls out to the pinctrl driver for claiming pins
unless the config has CONFIG_PINCTRL unset. IOW, if a pinctrl driver is
active, it must be visible to the GPIO driver.

Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Add the common data for all dk07 based boards.

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Tested-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds a DTS file for Sony Xperia Z1 Compact with support for
regulators, serial UART, eMMC/SD-card, USB, charger, backlight,
coincell and buttons.

Work based on arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts.

Signed-off-by: Attila Szöllősi <ata2001@airmail.cc>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This enables both USB ports as host with EHCI and UHCI
attached to them.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

This adds the USB controllers to the DT template of the
AST24xx and AST25xx SoCs.

This patch doesn't enable them by default on any board specific
.dts yet. This will be done when we have the necessary clock/reset
and pinmux support. In the meantime though, this will work if
u-boot configures things properly.

For the AST2400 I only added pinmux definition for port 1
which is dual USB1/USB2. There are additional USB1 only ports
that might require more work but I don't have HW to test at
hand so I'm leaving that to whoever cares.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

S2600WF is a Intel platform family with an ASPEED AST2500 BMC.

Signed-off-by: James Feist <james.feist@linux.intel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

The Inventec Lanyang is Power 9 platform with ast2500 BMC.

Signed-off-by: Brian Yang <yang.brianc.w@inventec.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

Initial introduction of Portwell Neptune family equipped with
Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a
ASPEED ast2500 BMC manufactured by Portwell. Specifically, This
adds the neptune platform device tree file including the flash
layout used by the neptune machines.

Signed-off-by: Amithash Prasad <amithash@fb.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

Set watchdog 2 to boot from the alternate flash chip when the watchdog
timer expires and the system is reset. This enables "brick protection."

Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

Enable gpio-keys events for the checkstop and water/air cooled
gpios for use by applications on the Witherspoon system.

Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

Add GPIO key to check presence of PCIE E2B.

Signed-off-by: Lei YU <mine260309@gmail.com>
Acked-by: Xo Wang <xow@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

Signed-off-by: Lei YU <mine260309@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

This patch adds support of external interrupt for
gpio[a..k], gpioz

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

This patch adds external interrupt (exti) support
on stm32mp157c SoC.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Fix "make dtbs W=1" warns about missing reg or ranges property.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html



Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html



Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Without this property, we get this boot warning:

"L2C: device tree omits to specify unified cache"

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Add interrupt-affinity property to fix below warning:
[    0.429642] CPU PMU: Failed to parse /soc/pmu/interrupt-affinity[0]

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Control the Chromecast's two LEDs using PWM instead of GPIO pins. This
allows for variable brightness.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>